OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 154

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 added t8039_notri hierarchy arniml 7158d 16h /t48/tags/rel_0_6_beta/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7159d 14h /t48/tags/rel_0_6_beta/
152 added hierarchy t8048_notri and system components package arniml 7160d 05h /t48/tags/rel_0_6_beta/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7160d 05h /t48/tags/rel_0_6_beta/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7160d 13h /t48/tags/rel_0_6_beta/
149 update arniml 7160d 13h /t48/tags/rel_0_6_beta/
148 initial check-in arniml 7160d 13h /t48/tags/rel_0_6_beta/
147 initial check-in for release 0.5 BETA arniml 7196d 14h /t48/tags/rel_0_6_beta/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7197d 14h /t48/tags/rel_0_6_beta/
145 remove PROG and end of XTAL2, see comment for details arniml 7197d 15h /t48/tags/rel_0_6_beta/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7197d 15h /t48/tags/rel_0_6_beta/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7197d 16h /t48/tags/rel_0_6_beta/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7197d 16h /t48/tags/rel_0_6_beta/
141 disable external memory to avoid conflicts with outl a, bus arniml 7197d 16h /t48/tags/rel_0_6_beta/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7197d 16h /t48/tags/rel_0_6_beta/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7199d 03h /t48/tags/rel_0_6_beta/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7199d 03h /t48/tags/rel_0_6_beta/
137 add link to COMPILE_LIST arniml 7236d 15h /t48/tags/rel_0_6_beta/
136 initial check-in arniml 7236d 15h /t48/tags/rel_0_6_beta/
135 add bug
PSENn Timing		 arniml 7241d 02h /t48/tags/rel_0_6_beta/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7241d 11h /t48/tags/rel_0_6_beta/
133 add checks for PSEN arniml 7241d 11h /t48/tags/rel_0_6_beta/
132 stop simulation upon assertion error arniml 7241d 11h /t48/tags/rel_0_6_beta/
131 update arniml 7241d 11h /t48/tags/rel_0_6_beta/
130 initial check-in arniml 7241d 11h /t48/tags/rel_0_6_beta/
129 cleanup copyright notice arniml 7303d 19h /t48/tags/rel_0_6_beta/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7310d 23h /t48/tags/rel_0_6_beta/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7311d 00h /t48/tags/rel_0_6_beta/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7311d 00h /t48/tags/rel_0_6_beta/
125 exclude from dump compare arniml 7311d 00h /t48/tags/rel_0_6_beta/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.