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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 157

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157 removed obsolete constant arniml 7184d 01h /t48/tags/rel_0_6_beta/
156 added hierarchy t8039_notri arniml 7184d 01h /t48/tags/rel_0_6_beta/
155 initial check-in arniml 7184d 01h /t48/tags/rel_0_6_beta/
154 added t8039_notri hierarchy arniml 7184d 01h /t48/tags/rel_0_6_beta/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7184d 23h /t48/tags/rel_0_6_beta/
152 added hierarchy t8048_notri and system components package arniml 7185d 14h /t48/tags/rel_0_6_beta/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7185d 14h /t48/tags/rel_0_6_beta/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7185d 22h /t48/tags/rel_0_6_beta/
149 update arniml 7185d 22h /t48/tags/rel_0_6_beta/
148 initial check-in arniml 7185d 22h /t48/tags/rel_0_6_beta/
147 initial check-in for release 0.5 BETA arniml 7221d 23h /t48/tags/rel_0_6_beta/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7222d 23h /t48/tags/rel_0_6_beta/
145 remove PROG and end of XTAL2, see comment for details arniml 7223d 01h /t48/tags/rel_0_6_beta/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7223d 01h /t48/tags/rel_0_6_beta/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7223d 01h /t48/tags/rel_0_6_beta/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7223d 01h /t48/tags/rel_0_6_beta/
141 disable external memory to avoid conflicts with outl a, bus arniml 7223d 01h /t48/tags/rel_0_6_beta/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7223d 01h /t48/tags/rel_0_6_beta/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7224d 12h /t48/tags/rel_0_6_beta/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7224d 12h /t48/tags/rel_0_6_beta/
137 add link to COMPILE_LIST arniml 7262d 00h /t48/tags/rel_0_6_beta/
136 initial check-in arniml 7262d 00h /t48/tags/rel_0_6_beta/
135 add bug
PSENn Timing		 arniml 7266d 11h /t48/tags/rel_0_6_beta/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7266d 20h /t48/tags/rel_0_6_beta/
133 add checks for PSEN arniml 7266d 20h /t48/tags/rel_0_6_beta/
132 stop simulation upon assertion error arniml 7266d 21h /t48/tags/rel_0_6_beta/
131 update arniml 7266d 21h /t48/tags/rel_0_6_beta/
130 initial check-in arniml 7266d 21h /t48/tags/rel_0_6_beta/
129 cleanup copyright notice arniml 7329d 04h /t48/tags/rel_0_6_beta/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7336d 08h /t48/tags/rel_0_6_beta/

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