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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 183

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Rev Log message Author Age Path
183 fix missing assignment to outclock arniml 6887d 23h /t48/tags/rel_0_6_beta/
182 intermediate version arniml 6967d 21h /t48/tags/rel_0_6_beta/
181 fix typo arniml 6968d 00h /t48/tags/rel_0_6_beta/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6976d 06h /t48/tags/rel_0_6_beta/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6976d 06h /t48/tags/rel_0_6_beta/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6977d 18h /t48/tags/rel_0_6_beta/
177 Implement db_dir_o glitch-safe arniml 6977d 18h /t48/tags/rel_0_6_beta/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6977d 18h /t48/tags/rel_0_6_beta/
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6978d 21h /t48/tags/rel_0_6_beta/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6978d 21h /t48/tags/rel_0_6_beta/
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6978d 21h /t48/tags/rel_0_6_beta/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7007d 18h /t48/tags/rel_0_6_beta/
171 remove obsolete output stack_high_o arniml 7008d 18h /t48/tags/rel_0_6_beta/
170 intermediate update arniml 7010d 00h /t48/tags/rel_0_6_beta/
169 initial check-in arniml 7010d 06h /t48/tags/rel_0_6_beta/
168 change address range of wb_master arniml 7010d 06h /t48/tags/rel_0_6_beta/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7010d 06h /t48/tags/rel_0_6_beta/
166 assign default for state_s arniml 7011d 21h /t48/tags/rel_0_6_beta/
165 add component wb_master.vhd arniml 7012d 21h /t48/tags/rel_0_6_beta/
164 initial check-in arniml 7012d 21h /t48/tags/rel_0_6_beta/
163 add bug
Wrong clock applied to T0		 arniml 7013d 20h /t48/tags/rel_0_6_beta/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7013d 20h /t48/tags/rel_0_6_beta/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7045d 00h /t48/tags/rel_0_6_beta/
160 add others to case statement arniml 7165d 20h /t48/tags/rel_0_6_beta/
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7165d 20h /t48/tags/rel_0_6_beta/
158 added hierarchies t8039_notri and t8048_notri arniml 7165d 20h /t48/tags/rel_0_6_beta/
157 removed obsolete constant arniml 7165d 21h /t48/tags/rel_0_6_beta/
156 added hierarchy t8039_notri arniml 7165d 21h /t48/tags/rel_0_6_beta/
155 initial check-in arniml 7165d 21h /t48/tags/rel_0_6_beta/
154 added t8039_notri hierarchy arniml 7165d 21h /t48/tags/rel_0_6_beta/

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