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[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 80

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Rev	Log message	Author	Age	Path
80	added if_timing	arniml	7403d 05h	/t48/tags/rel_0_6_beta/
79	add if_timing module	arniml	7403d 05h	/t48/tags/rel_0_6_beta/
78	adjust external timing of BUS	arniml	7403d 05h	/t48/tags/rel_0_6_beta/
77	move from std_logic_arith to numeric_std	arniml	7403d 21h	/t48/tags/rel_0_6_beta/
76	initial check-in	arniml	7404d 01h	/t48/tags/rel_0_6_beta/
75	remove obsolete design unit	arniml	7404d 01h	/t48/tags/rel_0_6_beta/
74	enhance pass/fail detection	arniml	7404d 10h	/t48/tags/rel_0_6_beta/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7404d 10h	/t48/tags/rel_0_6_beta/
72	removed superfluous signal from sensitivity list	arniml	7404d 10h	/t48/tags/rel_0_6_beta/
71	add T8039 and its testbench	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
70	clean test cell before make	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
69	fix name of istrobe	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
68	connect T0 and T1 to P1	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
67	initial check-in	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
66	add temporary workaround for GHDL 0.11	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
65	clean up sensitivity list	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
62	initial check-in	arniml	7410d 02h	/t48/tags/rel_0_6_beta/
61	expand script for dump compare	arniml	7411d 23h	/t48/tags/rel_0_6_beta/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7412d 23h	/t48/tags/rel_0_6_beta/
59	increment prescaler with MSTATE4	arniml	7412d 23h	/t48/tags/rel_0_6_beta/
58	add periodic interrupt	arniml	7412d 23h	/t48/tags/rel_0_6_beta/
57	abort if no interrupt occurs	arniml	7412d 23h	/t48/tags/rel_0_6_beta/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7414d 00h	/t48/tags/rel_0_6_beta/
55	add dependency to tb_behav_pack for decoder	arniml	7414d 00h	/t48/tags/rel_0_6_beta/
54	- add tb_istrobe_s	arniml	7414d 00h	/t48/tags/rel_0_6_beta/
53	make istrobe visible through testbench package	arniml	7414d 00h	/t48/tags/rel_0_6_beta/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7414d 00h	/t48/tags/rel_0_6_beta/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7414d 00h	/t48/tags/rel_0_6_beta/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] - Rev 80

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