OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 292

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5618d 10h /t48/tags/rel_0_6_beta/rtl/
258 This commit was manufactured by cvs2svn to create tag 'rel_0_6_beta'. 6588d 19h /t48/tags/rel_0_6_beta/rtl/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6891d 23h /t48/tags/rel_0_6_beta/rtl/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6891d 23h /t48/tags/rel_0_6_beta/rtl/
183 fix missing assignment to outclock arniml 6898d 03h /t48/tags/rel_0_6_beta/rtl/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6986d 10h /t48/tags/rel_0_6_beta/rtl/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6986d 10h /t48/tags/rel_0_6_beta/rtl/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6987d 22h /t48/tags/rel_0_6_beta/rtl/
177 Implement db_dir_o glitch-safe arniml 6987d 22h /t48/tags/rel_0_6_beta/rtl/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6987d 22h /t48/tags/rel_0_6_beta/rtl/
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6989d 01h /t48/tags/rel_0_6_beta/rtl/
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7017d 22h /t48/tags/rel_0_6_beta/rtl/
171 remove obsolete output stack_high_o arniml 7018d 22h /t48/tags/rel_0_6_beta/rtl/
169 initial check-in arniml 7020d 10h /t48/tags/rel_0_6_beta/rtl/
168 change address range of wb_master arniml 7020d 10h /t48/tags/rel_0_6_beta/rtl/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7020d 10h /t48/tags/rel_0_6_beta/rtl/
166 assign default for state_s arniml 7022d 01h /t48/tags/rel_0_6_beta/rtl/
165 add component wb_master.vhd arniml 7023d 00h /t48/tags/rel_0_6_beta/rtl/
164 initial check-in arniml 7023d 00h /t48/tags/rel_0_6_beta/rtl/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7024d 00h /t48/tags/rel_0_6_beta/rtl/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7055d 04h /t48/tags/rel_0_6_beta/rtl/
157 removed obsolete constant arniml 7176d 01h /t48/tags/rel_0_6_beta/rtl/
156 added hierarchy t8039_notri arniml 7176d 01h /t48/tags/rel_0_6_beta/rtl/
155 initial check-in arniml 7176d 01h /t48/tags/rel_0_6_beta/rtl/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7176d 22h /t48/tags/rel_0_6_beta/rtl/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7177d 21h /t48/tags/rel_0_6_beta/rtl/
149 update arniml 7177d 21h /t48/tags/rel_0_6_beta/rtl/
148 initial check-in arniml 7177d 21h /t48/tags/rel_0_6_beta/rtl/
145 remove PROG and end of XTAL2, see comment for details arniml 7215d 00h /t48/tags/rel_0_6_beta/rtl/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7215d 00h /t48/tags/rel_0_6_beta/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.