URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_6_beta/] [sw/] - Rev 131

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Rev	Log message	Author	Age	Path
131	update	arniml	7268d 18h	/t48/tags/rel_0_6_beta/sw/
130	initial check-in	arniml	7268d 18h	/t48/tags/rel_0_6_beta/sw/
127	+ log status of A11 properly during interrupt routines + trigger counter on negative edge of T1 instead of positive edge	arniml	7338d 06h	/t48/tags/rel_0_6_beta/sw/
126	+ specify hex file for external ROM on i8039 command line + support for no_dump_compare file in test cell	arniml	7338d 06h	/t48/tags/rel_0_6_beta/sw/
125	exclude from dump compare	arniml	7338d 06h	/t48/tags/rel_0_6_beta/sw/
124	fix wrong handling of MB after return from interrupt	arniml	7339d 04h	/t48/tags/rel_0_6_beta/sw/
123	support hex file for external ROM	arniml	7339d 04h	/t48/tags/rel_0_6_beta/sw/
122	test MB after return from interrupt	arniml	7339d 04h	/t48/tags/rel_0_6_beta/sw/
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7341d 21h	/t48/tags/rel_0_6_beta/sw/
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7382d 07h	/t48/tags/rel_0_6_beta/sw/
104	add white_box directory to test suite	arniml	7386d 04h	/t48/tags/rel_0_6_beta/sw/
102	update for changes in address space of external memory	arniml	7386d 04h	/t48/tags/rel_0_6_beta/sw/
99	initial check-in	arniml	7386d 04h	/t48/tags/rel_0_6_beta/sw/
97	initial check-in	arniml	7386d 05h	/t48/tags/rel_0_6_beta/sw/
96	select dedicated directorie(s) for regression	arniml	7387d 02h	/t48/tags/rel_0_6_beta/sw/
95	check counter inactivity	arniml	7387d 02h	/t48/tags/rel_0_6_beta/sw/
94	initial check-in	arniml	7387d 02h	/t48/tags/rel_0_6_beta/sw/
90	intial check-in	arniml	7387d 03h	/t48/tags/rel_0_6_beta/sw/
89	initial check-in	arniml	7400d 23h	/t48/tags/rel_0_6_beta/sw/
88	allow memory bank switching during interrupts	arniml	7402d 01h	/t48/tags/rel_0_6_beta/sw/
87	abort gracfullt if memory bank switching does not work	arniml	7402d 01h	/t48/tags/rel_0_6_beta/sw/
85	initial check-in	arniml	7402d 07h	/t48/tags/rel_0_6_beta/sw/
74	enhance pass/fail detection	arniml	7409d 07h	/t48/tags/rel_0_6_beta/sw/
70	clean test cell before make	arniml	7414d 23h	/t48/tags/rel_0_6_beta/sw/
69	fix name of istrobe	arniml	7414d 23h	/t48/tags/rel_0_6_beta/sw/
61	expand script for dump compare	arniml	7416d 20h	/t48/tags/rel_0_6_beta/sw/
58	add periodic interrupt	arniml	7417d 20h	/t48/tags/rel_0_6_beta/sw/
57	abort if no interrupt occurs	arniml	7417d 20h	/t48/tags/rel_0_6_beta/sw/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7418d 22h	/t48/tags/rel_0_6_beta/sw/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7418d 22h	/t48/tags/rel_0_6_beta/sw/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [sw/] - Rev 131

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