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[/] [t48/] [tags/] [rel_1_0/] - Rev 124

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Rev Log message Author Age Path
124 fix wrong handling of MB after return from interrupt arniml 7316d 01h /t48/tags/rel_1_0/
123 support hex file for external ROM arniml 7316d 01h /t48/tags/rel_1_0/
122 test MB after return from interrupt arniml 7316d 01h /t48/tags/rel_1_0/
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7318d 18h /t48/tags/rel_1_0/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7318d 18h /t48/tags/rel_1_0/
119 add int_in_progress_o to entity of int module arniml 7318d 18h /t48/tags/rel_1_0/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7318d 18h /t48/tags/rel_1_0/
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7319d 19h /t48/tags/rel_1_0/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7347d 19h /t48/tags/rel_1_0/
115 extend description arniml 7348d 23h /t48/tags/rel_1_0/
114 initial check-in arniml 7352d 19h /t48/tags/rel_1_0/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7359d 04h /t48/tags/rel_1_0/
112 update tb_behav_c0 for new ROM layout arniml 7359d 04h /t48/tags/rel_1_0/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7359d 04h /t48/tags/rel_1_0/
110 exchange syn_rom for lpm_rom arniml 7359d 04h /t48/tags/rel_1_0/
109 add new bug for release 0.1 BETA arniml 7359d 17h /t48/tags/rel_1_0/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7359d 17h /t48/tags/rel_1_0/
107 tie EA to '1' arniml 7359d 17h /t48/tags/rel_1_0/
106 clean-up use of ea_i arniml 7359d 17h /t48/tags/rel_1_0/
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7362d 03h /t48/tags/rel_1_0/
104 add white_box directory to test suite arniml 7363d 00h /t48/tags/rel_1_0/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7363d 00h /t48/tags/rel_1_0/
102 update for changes in address space of external memory arniml 7363d 01h /t48/tags/rel_1_0/
101 assert p2_read_p2_o when expander port is read arniml 7363d 01h /t48/tags/rel_1_0/
100 reorder data_o generation arniml 7363d 01h /t48/tags/rel_1_0/
99 initial check-in arniml 7363d 01h /t48/tags/rel_1_0/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7363d 01h /t48/tags/rel_1_0/
97 initial check-in arniml 7363d 01h /t48/tags/rel_1_0/
96 select dedicated directorie(s) for regression arniml 7363d 23h /t48/tags/rel_1_0/
95 check counter inactivity arniml 7363d 23h /t48/tags/rel_1_0/

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