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[/] [t48/] [tags/] [rel_1_0/] - Rev 30

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Rev Log message Author Age Path
30 connect prog_n_o arniml 7414d 04h /t48/tags/rel_1_0/
29 take auxiliary carry from direct ALU connection arniml 7414d 04h /t48/tags/rel_1_0/
28 update wiring for DA support arniml 7414d 04h /t48/tags/rel_1_0/
27 implemented mnemonic DA arniml 7414d 05h /t48/tags/rel_1_0/
26 support for DA instruction arniml 7414d 05h /t48/tags/rel_1_0/
25 initial check-in arniml 7414d 05h /t48/tags/rel_1_0/
24 connect control signal for Port 2 expander arniml 7414d 13h /t48/tags/rel_1_0/
23 rework Port 2 expander handling arniml 7414d 13h /t48/tags/rel_1_0/
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7414d 13h /t48/tags/rel_1_0/
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A
arniml 7414d 13h /t48/tags/rel_1_0/
20 move code for PROG out of if-branch for xtal3_s arniml 7414d 13h /t48/tags/rel_1_0/
19 enhance simulation result string arniml 7416d 03h /t48/tags/rel_1_0/
18 fix constant format arniml 7416d 03h /t48/tags/rel_1_0/
17 fix test arniml 7416d 03h /t48/tags/rel_1_0/
16 fix header arniml 7416d 03h /t48/tags/rel_1_0/
15 initial check-in arniml 7417d 02h /t48/tags/rel_1_0/
14 initial check-in arniml 7417d 03h /t48/tags/rel_1_0/
12 Imported sources arniml 7417d 03h /t48/tags/rel_1_0/
11 add description arniml 7417d 04h /t48/tags/rel_1_0/
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7418d 02h /t48/tags/rel_1_0/
9 initial check-in arniml 7418d 02h /t48/tags/rel_1_0/
8 initial check-in arniml 7418d 04h /t48/tags/rel_1_0/
7 initial check-in arniml 7418d 04h /t48/tags/rel_1_0/
6 moved to system directory arniml 7418d 04h /t48/tags/rel_1_0/
5 initial check-in arniml 7419d 04h /t48/tags/rel_1_0/
4 initial check-in arniml 7419d 04h /t48/tags/rel_1_0/
3 bummer arniml 7419d 04h /t48/tags/rel_1_0/
2 initial check-in arniml 7419d 04h /t48/tags/rel_1_0/
1 Standard project directories initialized by cvs2svn. 7419d 04h /t48/tags/rel_1_0/

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