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[/] [t48/] [tags/] [rel_1_0/] - Rev 78

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Rev	Log message	Author	Age	Path
78	adjust external timing of BUS	arniml	7385d 14h	/t48/tags/rel_1_0/
77	move from std_logic_arith to numeric_std	arniml	7386d 06h	/t48/tags/rel_1_0/
76	initial check-in	arniml	7386d 10h	/t48/tags/rel_1_0/
75	remove obsolete design unit	arniml	7386d 10h	/t48/tags/rel_1_0/
74	enhance pass/fail detection	arniml	7386d 19h	/t48/tags/rel_1_0/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7386d 19h	/t48/tags/rel_1_0/
72	removed superfluous signal from sensitivity list	arniml	7386d 19h	/t48/tags/rel_1_0/
71	add T8039 and its testbench	arniml	7392d 11h	/t48/tags/rel_1_0/
70	clean test cell before make	arniml	7392d 11h	/t48/tags/rel_1_0/
69	fix name of istrobe	arniml	7392d 11h	/t48/tags/rel_1_0/
68	connect T0 and T1 to P1	arniml	7392d 11h	/t48/tags/rel_1_0/
67	initial check-in	arniml	7392d 11h	/t48/tags/rel_1_0/
66	add temporary workaround for GHDL 0.11	arniml	7392d 11h	/t48/tags/rel_1_0/
65	clean up sensitivity list	arniml	7392d 11h	/t48/tags/rel_1_0/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7392d 11h	/t48/tags/rel_1_0/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7392d 11h	/t48/tags/rel_1_0/
62	initial check-in	arniml	7392d 11h	/t48/tags/rel_1_0/
61	expand script for dump compare	arniml	7394d 08h	/t48/tags/rel_1_0/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7395d 08h	/t48/tags/rel_1_0/
59	increment prescaler with MSTATE4	arniml	7395d 08h	/t48/tags/rel_1_0/
58	add periodic interrupt	arniml	7395d 08h	/t48/tags/rel_1_0/
57	abort if no interrupt occurs	arniml	7395d 08h	/t48/tags/rel_1_0/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7396d 09h	/t48/tags/rel_1_0/
55	add dependency to tb_behav_pack for decoder	arniml	7396d 09h	/t48/tags/rel_1_0/
54	- add tb_istrobe_s	arniml	7396d 09h	/t48/tags/rel_1_0/
53	make istrobe visible through testbench package	arniml	7396d 09h	/t48/tags/rel_1_0/
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7396d 09h	/t48/tags/rel_1_0/
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7396d 09h	/t48/tags/rel_1_0/
49	Imported sources	arniml	7401d 11h	/t48/tags/rel_1_0/
48	update copyright notice	arniml	7401d 11h	/t48/tags/rel_1_0/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] - Rev 78

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