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[/] [t48/] [tags/] [rel_1_0/] [bench/] [vhdl/] - Rev 292

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292 New directory structure. root 5608d 06h /t48/tags/rel_1_0/bench/vhdl/
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6420d 16h /t48/tags/rel_1_0/bench/vhdl/
248 initial check-in arniml 6578d 14h /t48/tags/rel_1_0/bench/vhdl/
247 initial check-in arniml 6578d 17h /t48/tags/rel_1_0/bench/vhdl/
240 comment added about lower 1k of external ROM arniml 6598d 15h /t48/tags/rel_1_0/bench/vhdl/
234 cleanup & enhance external access arniml 6600d 15h /t48/tags/rel_1_0/bench/vhdl/
233 added external ROM arniml 6600d 15h /t48/tags/rel_1_0/bench/vhdl/
228 replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom arniml 6601d 14h /t48/tags/rel_1_0/bench/vhdl/
224 initial check-in arniml 6601d 15h /t48/tags/rel_1_0/bench/vhdl/
220 new input xtal_en_i arniml 6602d 15h /t48/tags/rel_1_0/bench/vhdl/
202 fix address assignment arniml 6832d 18h /t48/tags/rel_1_0/bench/vhdl/
201 split low impedance markers for P2 arniml 6832d 18h /t48/tags/rel_1_0/bench/vhdl/
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6832d 18h /t48/tags/rel_1_0/bench/vhdl/
183 fix missing assignment to outclock arniml 6887d 22h /t48/tags/rel_1_0/bench/vhdl/
160 add others to case statement arniml 7165d 20h /t48/tags/rel_1_0/bench/vhdl/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7204d 20h /t48/tags/rel_1_0/bench/vhdl/
133 add checks for PSEN arniml 7248d 15h /t48/tags/rel_1_0/bench/vhdl/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7362d 04h /t48/tags/rel_1_0/bench/vhdl/
110 exchange syn_rom for lpm_rom arniml 7362d 04h /t48/tags/rel_1_0/bench/vhdl/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7366d 01h /t48/tags/rel_1_0/bench/vhdl/
83 connect if_timing to P2 output of T48 arniml 7387d 19h /t48/tags/rel_1_0/bench/vhdl/
82 check expander timings arniml 7387d 19h /t48/tags/rel_1_0/bench/vhdl/
81 initial check-in arniml 7387d 23h /t48/tags/rel_1_0/bench/vhdl/
80 added if_timing arniml 7387d 23h /t48/tags/rel_1_0/bench/vhdl/
68 connect T0 and T1 to P1 arniml 7394d 20h /t48/tags/rel_1_0/bench/vhdl/
67 initial check-in arniml 7394d 20h /t48/tags/rel_1_0/bench/vhdl/
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7398d 19h /t48/tags/rel_1_0/bench/vhdl/
33 rename pX_limp to pX_low_imp arniml 7414d 20h /t48/tags/rel_1_0/bench/vhdl/
30 connect prog_n_o arniml 7415d 18h /t48/tags/rel_1_0/bench/vhdl/
19 enhance simulation result string arniml 7417d 17h /t48/tags/rel_1_0/bench/vhdl/

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