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[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 128

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Rev	Log message	Author	Age	Path
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7373d 16h	/t48/tags/rel_1_0/rtl/
120	Fix bug report: "Program Memory bank can be switched during interrupt" int module emits int_in_progress signal that is used inside the decoder to hold mb low for JMP and CALL during interrupts	arniml	7377d 08h	/t48/tags/rel_1_0/rtl/
119	add int_in_progress_o to entity of int module	arniml	7377d 08h	/t48/tags/rel_1_0/rtl/
108	Fix for: External Program Memory ignored when EA = 0	arniml	7418d 07h	/t48/tags/rel_1_0/rtl/
107	tie EA to '1'	arniml	7418d 08h	/t48/tags/rel_1_0/rtl/
106	clean-up use of ea_i	arniml	7418d 08h	/t48/tags/rel_1_0/rtl/
101	assert p2_read_p2_o when expander port is read	arniml	7421d 15h	/t48/tags/rel_1_0/rtl/
100	reorder data_o generation	arniml	7421d 15h	/t48/tags/rel_1_0/rtl/
98	Fix bug "ANL and ORL to P1/P2 read port status instead of port output register"	arniml	7421d 16h	/t48/tags/rel_1_0/rtl/
92	work around bug in Quartus II 4.0	arniml	7422d 14h	/t48/tags/rel_1_0/rtl/
91	fix edge detector bug for counter	arniml	7422d 14h	/t48/tags/rel_1_0/rtl/
86	update notice about expander port instructions	arniml	7437d 17h	/t48/tags/rel_1_0/rtl/
78	adjust external timing of BUS	arniml	7443d 13h	/t48/tags/rel_1_0/rtl/
77	move from std_logic_arith to numeric_std	arniml	7444d 06h	/t48/tags/rel_1_0/rtl/
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7444d 18h	/t48/tags/rel_1_0/rtl/
72	removed superfluous signal from sensitivity list	arniml	7444d 18h	/t48/tags/rel_1_0/rtl/
66	add temporary workaround for GHDL 0.11	arniml	7450d 10h	/t48/tags/rel_1_0/rtl/
65	clean up sensitivity list	arniml	7450d 10h	/t48/tags/rel_1_0/rtl/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7450d 10h	/t48/tags/rel_1_0/rtl/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7450d 10h	/t48/tags/rel_1_0/rtl/
62	initial check-in	arniml	7450d 11h	/t48/tags/rel_1_0/rtl/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7453d 07h	/t48/tags/rel_1_0/rtl/
59	increment prescaler with MSTATE4	arniml	7453d 07h	/t48/tags/rel_1_0/rtl/
54	- add tb_istrobe_s	arniml	7454d 09h	/t48/tags/rel_1_0/rtl/
53	make istrobe visible through testbench package	arniml	7454d 09h	/t48/tags/rel_1_0/rtl/
45	remove unused signals	arniml	7461d 07h	/t48/tags/rel_1_0/rtl/
44	default assignment for aux_carry_o	arniml	7461d 08h	/t48/tags/rel_1_0/rtl/
43	fix sensitivity list	arniml	7462d 09h	/t48/tags/rel_1_0/rtl/
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7462d 11h	/t48/tags/rel_1_0/rtl/
38	add measures to implement XCHD	arniml	7464d 15h	/t48/tags/rel_1_0/rtl/

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] - Rev 128

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