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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 168

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Rev Log message Author Age Path
168 change address range of wb_master arniml 7003d 11h /t48/tags/rel_1_0/rtl/vhdl/
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7003d 11h /t48/tags/rel_1_0/rtl/vhdl/
166 assign default for state_s arniml 7005d 03h /t48/tags/rel_1_0/rtl/vhdl/
165 add component wb_master.vhd arniml 7006d 02h /t48/tags/rel_1_0/rtl/vhdl/
164 initial check-in arniml 7006d 02h /t48/tags/rel_1_0/rtl/vhdl/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7007d 02h /t48/tags/rel_1_0/rtl/vhdl/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7038d 06h /t48/tags/rel_1_0/rtl/vhdl/
157 removed obsolete constant arniml 7159d 02h /t48/tags/rel_1_0/rtl/vhdl/
156 added hierarchy t8039_notri arniml 7159d 02h /t48/tags/rel_1_0/rtl/vhdl/
155 initial check-in arniml 7159d 02h /t48/tags/rel_1_0/rtl/vhdl/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7160d 00h /t48/tags/rel_1_0/rtl/vhdl/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7160d 23h /t48/tags/rel_1_0/rtl/vhdl/
149 update arniml 7160d 23h /t48/tags/rel_1_0/rtl/vhdl/
148 initial check-in arniml 7160d 23h /t48/tags/rel_1_0/rtl/vhdl/
145 remove PROG and end of XTAL2, see comment for details arniml 7198d 01h /t48/tags/rel_1_0/rtl/vhdl/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7198d 01h /t48/tags/rel_1_0/rtl/vhdl/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7198d 02h /t48/tags/rel_1_0/rtl/vhdl/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7198d 02h /t48/tags/rel_1_0/rtl/vhdl/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7199d 13h /t48/tags/rel_1_0/rtl/vhdl/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7241d 21h /t48/tags/rel_1_0/rtl/vhdl/
129 cleanup copyright notice arniml 7304d 05h /t48/tags/rel_1_0/rtl/vhdl/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7311d 09h /t48/tags/rel_1_0/rtl/vhdl/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7315d 01h /t48/tags/rel_1_0/rtl/vhdl/
119 add int_in_progress_o to entity of int module arniml 7315d 01h /t48/tags/rel_1_0/rtl/vhdl/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7356d 00h /t48/tags/rel_1_0/rtl/vhdl/
107 tie EA to '1' arniml 7356d 00h /t48/tags/rel_1_0/rtl/vhdl/
106 clean-up use of ea_i arniml 7356d 00h /t48/tags/rel_1_0/rtl/vhdl/
101 assert p2_read_p2_o when expander port is read arniml 7359d 07h /t48/tags/rel_1_0/rtl/vhdl/
100 reorder data_o generation arniml 7359d 07h /t48/tags/rel_1_0/rtl/vhdl/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7359d 08h /t48/tags/rel_1_0/rtl/vhdl/

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