OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] - Rev 142

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7201d 21h /t48/tags/rel_1_1/
141 disable external memory to avoid conflicts with outl a, bus arniml 7201d 21h /t48/tags/rel_1_1/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7201d 21h /t48/tags/rel_1_1/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7203d 07h /t48/tags/rel_1_1/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7203d 07h /t48/tags/rel_1_1/
137 add link to COMPILE_LIST arniml 7240d 20h /t48/tags/rel_1_1/
136 initial check-in arniml 7240d 20h /t48/tags/rel_1_1/
135 add bug
PSENn Timing		 arniml 7245d 06h /t48/tags/rel_1_1/
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7245d 16h /t48/tags/rel_1_1/
133 add checks for PSEN arniml 7245d 16h /t48/tags/rel_1_1/
132 stop simulation upon assertion error arniml 7245d 16h /t48/tags/rel_1_1/
131 update arniml 7245d 16h /t48/tags/rel_1_1/
130 initial check-in arniml 7245d 16h /t48/tags/rel_1_1/
129 cleanup copyright notice arniml 7308d 00h /t48/tags/rel_1_1/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7315d 03h /t48/tags/rel_1_1/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7315d 04h /t48/tags/rel_1_1/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7315d 04h /t48/tags/rel_1_1/
125 exclude from dump compare arniml 7315d 04h /t48/tags/rel_1_1/
124 fix wrong handling of MB after return from interrupt arniml 7316d 02h /t48/tags/rel_1_1/
123 support hex file for external ROM arniml 7316d 02h /t48/tags/rel_1_1/
122 test MB after return from interrupt arniml 7316d 02h /t48/tags/rel_1_1/
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7318d 19h /t48/tags/rel_1_1/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7318d 19h /t48/tags/rel_1_1/
119 add int_in_progress_o to entity of int module arniml 7318d 19h /t48/tags/rel_1_1/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7318d 19h /t48/tags/rel_1_1/
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7319d 20h /t48/tags/rel_1_1/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7347d 20h /t48/tags/rel_1_1/
115 extend description arniml 7349d 00h /t48/tags/rel_1_1/
114 initial check-in arniml 7352d 20h /t48/tags/rel_1_1/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7359d 05h /t48/tags/rel_1_1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.