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[/] [t48/] [tags/] [rel_1_1/] - Rev 166

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Rev Log message Author Age Path
166 assign default for state_s arniml 7008d 12h /t48/tags/rel_1_1/
165 add component wb_master.vhd arniml 7009d 11h /t48/tags/rel_1_1/
164 initial check-in arniml 7009d 11h /t48/tags/rel_1_1/
163 add bug
Wrong clock applied to T0		 arniml 7010d 11h /t48/tags/rel_1_1/
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7010d 11h /t48/tags/rel_1_1/
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7041d 15h /t48/tags/rel_1_1/
160 add others to case statement arniml 7162d 11h /t48/tags/rel_1_1/
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7162d 11h /t48/tags/rel_1_1/
158 added hierarchies t8039_notri and t8048_notri arniml 7162d 11h /t48/tags/rel_1_1/
157 removed obsolete constant arniml 7162d 11h /t48/tags/rel_1_1/
156 added hierarchy t8039_notri arniml 7162d 11h /t48/tags/rel_1_1/
155 initial check-in arniml 7162d 11h /t48/tags/rel_1_1/
154 added t8039_notri hierarchy arniml 7162d 11h /t48/tags/rel_1_1/
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7163d 09h /t48/tags/rel_1_1/
152 added hierarchy t8048_notri and system components package arniml 7164d 00h /t48/tags/rel_1_1/
151 added hierarchy t8048_notri and components package for t48 systems arniml 7164d 00h /t48/tags/rel_1_1/
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7164d 08h /t48/tags/rel_1_1/
149 update arniml 7164d 08h /t48/tags/rel_1_1/
148 initial check-in arniml 7164d 08h /t48/tags/rel_1_1/
147 initial check-in for release 0.5 BETA arniml 7200d 09h /t48/tags/rel_1_1/
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7201d 09h /t48/tags/rel_1_1/
145 remove PROG and end of XTAL2, see comment for details arniml 7201d 11h /t48/tags/rel_1_1/
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7201d 11h /t48/tags/rel_1_1/
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7201d 11h /t48/tags/rel_1_1/
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7201d 12h /t48/tags/rel_1_1/
141 disable external memory to avoid conflicts with outl a, bus arniml 7201d 12h /t48/tags/rel_1_1/
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7201d 12h /t48/tags/rel_1_1/
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7202d 22h /t48/tags/rel_1_1/
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7202d 22h /t48/tags/rel_1_1/
137 add link to COMPILE_LIST arniml 7240d 10h /t48/tags/rel_1_1/

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