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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] - Rev 205

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Rev	Log message	Author	Age	Path
205	operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3	arniml	6851d 12h	/t48/tags/rel_1_1/rtl/vhdl/
204	* suppress p2_output_pch_o when p2_output_exp is active * wire xtal_i to interrupt module	arniml	6851d 12h	/t48/tags/rel_1_1/rtl/vhdl/
203	* shift assertion of ALE and PROG to xtal3 * correct change of revision 1.8	arniml	6851d 13h	/t48/tags/rel_1_1/rtl/vhdl/
195	Suppress assertion of bus_read_bus_s when interrupt is pending. This should fix bug report "PROBLEM WHEN INT AND JMP"	arniml	6853d 00h	/t48/tags/rel_1_1/rtl/vhdl/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6900d 13h	/t48/tags/rel_1_1/rtl/vhdl/
187	Fix bug reports: "Target address of JMP to Program Memory Bank 1 corrupted by interrupt" "Return address of CALL to Program Memory Bank 1 corrupted by interrupt" int_in_progress_o was active one cycle before int_pending_o is asserted. this confused the mb multiplexer which determines the state of the memory bank selection flag	arniml	6900d 13h	/t48/tags/rel_1_1/rtl/vhdl/
183	fix missing assignment to outclock	arniml	6906d 16h	/t48/tags/rel_1_1/rtl/vhdl/
180	introduce prefix 't48_' for wb_master entity and configuration	arniml	6995d 00h	/t48/tags/rel_1_1/rtl/vhdl/
179	introduce prefix 't48_' for all packages, entities and configurations	arniml	6995d 00h	/t48/tags/rel_1_1/rtl/vhdl/
178	Move latching of BUS to MSTATE2 -> sample BUS at the end of RD'	arniml	6996d 12h	/t48/tags/rel_1_1/rtl/vhdl/
177	Implement db_dir_o glitch-safe	arniml	6996d 12h	/t48/tags/rel_1_1/rtl/vhdl/
176	Use en_clk_i instead of xtal3_s for generation of external signals. This is required when the core runs with full xtal clock instead of xtal/3 (xtal_div_3_g = 0).	arniml	6996d 12h	/t48/tags/rel_1_1/rtl/vhdl/
174	fix bug report "MSB of Program Counter changed upon PC increment"	arniml	6997d 15h	/t48/tags/rel_1_1/rtl/vhdl/
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7026d 11h	/t48/tags/rel_1_1/rtl/vhdl/
171	remove obsolete output stack_high_o	arniml	7027d 11h	/t48/tags/rel_1_1/rtl/vhdl/
169	initial check-in	arniml	7028d 23h	/t48/tags/rel_1_1/rtl/vhdl/
168	change address range of wb_master	arniml	7028d 23h	/t48/tags/rel_1_1/rtl/vhdl/
167	simplify address range: - configuration range - Wishbone range	arniml	7028d 23h	/t48/tags/rel_1_1/rtl/vhdl/
166	assign default for state_s	arniml	7030d 15h	/t48/tags/rel_1_1/rtl/vhdl/
165	add component wb_master.vhd	arniml	7031d 14h	/t48/tags/rel_1_1/rtl/vhdl/
164	initial check-in	arniml	7031d 14h	/t48/tags/rel_1_1/rtl/vhdl/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	7032d 14h	/t48/tags/rel_1_1/rtl/vhdl/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7063d 18h	/t48/tags/rel_1_1/rtl/vhdl/
157	removed obsolete constant	arniml	7184d 14h	/t48/tags/rel_1_1/rtl/vhdl/
156	added hierarchy t8039_notri	arniml	7184d 14h	/t48/tags/rel_1_1/rtl/vhdl/
155	initial check-in	arniml	7184d 14h	/t48/tags/rel_1_1/rtl/vhdl/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7185d 12h	/t48/tags/rel_1_1/rtl/vhdl/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7186d 11h	/t48/tags/rel_1_1/rtl/vhdl/
149	update	arniml	7186d 11h	/t48/tags/rel_1_1/rtl/vhdl/
148	initial check-in	arniml	7186d 11h	/t48/tags/rel_1_1/rtl/vhdl/

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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] - Rev 205

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