OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 select dedicated directorie(s) for regression arniml 7391d 12h /t48/tags/rel_1_1/sw/
95 check counter inactivity arniml 7391d 12h /t48/tags/rel_1_1/sw/
94 initial check-in arniml 7391d 12h /t48/tags/rel_1_1/sw/
90 intial check-in arniml 7391d 13h /t48/tags/rel_1_1/sw/
89 initial check-in arniml 7405d 09h /t48/tags/rel_1_1/sw/
88 allow memory bank switching during interrupts arniml 7406d 11h /t48/tags/rel_1_1/sw/
87 abort gracfullt if memory bank switching does not work arniml 7406d 11h /t48/tags/rel_1_1/sw/
85 initial check-in arniml 7406d 16h /t48/tags/rel_1_1/sw/
74 enhance pass/fail detection arniml 7413d 17h /t48/tags/rel_1_1/sw/
70 clean test cell before make arniml 7419d 09h /t48/tags/rel_1_1/sw/
69 fix name of istrobe arniml 7419d 09h /t48/tags/rel_1_1/sw/
61 expand script for dump compare arniml 7421d 06h /t48/tags/rel_1_1/sw/
58 add periodic interrupt arniml 7422d 06h /t48/tags/rel_1_1/sw/
57 abort if no interrupt occurs arniml 7422d 06h /t48/tags/rel_1_1/sw/
52 + fix bug in PSW[3]
+ read SP properly for dump		 arniml 7423d 07h /t48/tags/rel_1_1/sw/
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents		 arniml 7423d 07h /t48/tags/rel_1_1/sw/
49 Imported sources arniml 7428d 09h /t48/tags/rel_1_1/sw/
48 update copyright notice arniml 7428d 09h /t48/tags/rel_1_1/sw/
47 initial check-in arniml 7428d 09h /t48/tags/rel_1_1/sw/
46 fix test arniml 7430d 06h /t48/tags/rel_1_1/sw/
42 change test values that match better to the test case arniml 7431d 10h /t48/tags/rel_1_1/sw/
41 expand PATH arniml 7431d 10h /t48/tags/rel_1_1/sw/
39 initial check-in arniml 7433d 14h /t48/tags/rel_1_1/sw/
36 make calculation of expected value more readable arniml 7433d 15h /t48/tags/rel_1_1/sw/
35 initial check-in arniml 7436d 08h /t48/tags/rel_1_1/sw/
34 fix test wrt AC arniml 7439d 08h /t48/tags/rel_1_1/sw/
25 initial check-in arniml 7440d 07h /t48/tags/rel_1_1/sw/
18 fix constant format arniml 7442d 06h /t48/tags/rel_1_1/sw/
17 fix test arniml 7442d 06h /t48/tags/rel_1_1/sw/
15 initial check-in arniml 7443d 05h /t48/tags/rel_1_1/sw/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.