OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] [verif/] - Rev 292

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5604d 03h /t48/tags/rel_1_1/sw/verif/
289 This commit was manufactured by cvs2svn to create tag 'rel_1_1'. 5917d 14h /t48/tags/rel_1_1/sw/verif/
268 io expander not suitable for dump compare arniml 6571d 14h /t48/tags/rel_1_1/sw/verif/
266 cell contains io expander tests arniml 6571d 14h /t48/tags/rel_1_1/sw/verif/
265 tagging changed for io expander simulation arniml 6571d 14h /t48/tags/rel_1_1/sw/verif/
264 initial check-in arniml 6571d 14h /t48/tags/rel_1_1/sw/verif/
246 initial check-in arniml 6576d 13h /t48/tags/rel_1_1/sw/verif/
245 initial check-in arniml 6576d 14h /t48/tags/rel_1_1/sw/verif/
239 adapt t48 external ROM offset arniml 6594d 12h /t48/tags/rel_1_1/sw/verif/
238 initial check-in arniml 6594d 12h /t48/tags/rel_1_1/sw/verif/
237 initial check-in arniml 6594d 12h /t48/tags/rel_1_1/sw/verif/
236 initial check-in arniml 6594d 13h /t48/tags/rel_1_1/sw/verif/
229 rework hex/simulation targets arniml 6597d 12h /t48/tags/rel_1_1/sw/verif/
199 initial check-in arniml 6828d 16h /t48/tags/rel_1_1/sw/verif/
194 initial check-in arniml 6830d 03h /t48/tags/rel_1_1/sw/verif/
185 initial check-in arniml 6883d 15h /t48/tags/rel_1_1/sw/verif/
184 initial check-in arniml 6883d 17h /t48/tags/rel_1_1/sw/verif/
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"
arniml 6974d 18h /t48/tags/rel_1_1/sw/verif/
141 disable external memory to avoid conflicts with outl a, bus arniml 7200d 18h /t48/tags/rel_1_1/sw/verif/
131 update arniml 7244d 13h /t48/tags/rel_1_1/sw/verif/
130 initial check-in arniml 7244d 13h /t48/tags/rel_1_1/sw/verif/
125 exclude from dump compare arniml 7314d 01h /t48/tags/rel_1_1/sw/verif/
122 test MB after return from interrupt arniml 7314d 23h /t48/tags/rel_1_1/sw/verif/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7317d 16h /t48/tags/rel_1_1/sw/verif/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7358d 02h /t48/tags/rel_1_1/sw/verif/
102 update for changes in address space of external memory arniml 7361d 22h /t48/tags/rel_1_1/sw/verif/
99 initial check-in arniml 7361d 23h /t48/tags/rel_1_1/sw/verif/
97 initial check-in arniml 7361d 23h /t48/tags/rel_1_1/sw/verif/
95 check counter inactivity arniml 7362d 21h /t48/tags/rel_1_1/sw/verif/
94 initial check-in arniml 7362d 21h /t48/tags/rel_1_1/sw/verif/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.