URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4/] [rtl/] - Rev 271

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
271	initial check-in	arniml	6473d 05h	/t48/tags/rel_1_4/rtl/
270	fix component name	arniml	6473d 06h	/t48/tags/rel_1_4/rtl/
262	name keyword added	arniml	6608d 17h	/t48/tags/rel_1_4/rtl/
261	* name tag added * restriction concerning expander port removed	arniml	6608d 17h	/t48/tags/rel_1_4/rtl/
249	Fix bug report "Deassertion of PROG too early" PROG is deasserted at end of XTAL3 now	arniml	6608d 17h	/t48/tags/rel_1_4/rtl/
247	initial check-in	arniml	6608d 19h	/t48/tags/rel_1_4/rtl/
231	obsoleted by new memory concept	arniml	6631d 17h	/t48/tags/rel_1_4/rtl/
227	replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom	arniml	6631d 17h	/t48/tags/rel_1_4/rtl/
226	replaced syn_ram with generic_ram_ena	arniml	6631d 17h	/t48/tags/rel_1_4/rtl/
225	replaced syn_rom and syn_ram with t48_rom and generic_ram_ena	arniml	6631d 17h	/t48/tags/rel_1_4/rtl/
224	initial check-in	arniml	6631d 17h	/t48/tags/rel_1_4/rtl/
222	add note about clock enable for data memory RAM macro	arniml	6632d 17h	/t48/tags/rel_1_4/rtl/
221	new input xtal_en_i	arniml	6632d 17h	/t48/tags/rel_1_4/rtl/
220	new input xtal_en_i	arniml	6632d 17h	/t48/tags/rel_1_4/rtl/
219	new input xtal_en_i gates xtal_i base clock	arniml	6632d 17h	/t48/tags/rel_1_4/rtl/
216	assign clk_i to outclock	arniml	6849d 21h	/t48/tags/rel_1_4/rtl/
215	suppress p2_output_pch_o when MOVX operation is accessing the external memory	arniml	6849d 21h	/t48/tags/rel_1_4/rtl/
214	fix sensitivity list	arniml	6856d 22h	/t48/tags/rel_1_4/rtl/
213	properly drive P1 and P2 with low impedance markers	arniml	6861d 18h	/t48/tags/rel_1_4/rtl/
211	wire signals for P2 low impedance marker issue	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
210	entity changes for P2 low impedance marker issue	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
209	entity changes for P2 low impedance issue	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
208	wire signals for P2 low impeddance marker issue	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
207	entity changes for P2 low impedance trigger issue	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
206	* change low impedance markers for P2 separate marker for low and high part * p2_o output is also registered to prevent combinational output to pads	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
205	operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
204	* suppress p2_output_pch_o when p2_output_exp is active * wire xtal_i to interrupt module	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
203	* shift assertion of ALE and PROG to xtal3 * correct change of revision 1.8	arniml	6862d 20h	/t48/tags/rel_1_4/rtl/
195	Suppress assertion of bus_read_bus_s when interrupt is pending. This should fix bug report "PROBLEM WHEN INT AND JMP"	arniml	6864d 08h	/t48/tags/rel_1_4/rtl/
188	move check for int_pending_s into ea_i_='0' branch this fixes a glitch on PCH when an interrutp occurs during external program memory fetch	arniml	6911d 21h	/t48/tags/rel_1_4/rtl/

Browse

Tools

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4/] [rtl/] - Rev 271

Filtering Options