| Rev |
Log message |
Author |
Age |
Path |
| 96 |
IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation. |
creep |
5619d 12h |
/t6507lp/ |
| 95 |
IDX addressing mode is also 100%, coded and simulated. |
creep |
5619d 16h |
/t6507lp/ |
| 94 |
Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles. |
creep |
5620d 12h |
/t6507lp/ |
| 93 |
Opcode for BNE was wrong. |
creep |
5620d 14h |
/t6507lp/ |
| 92 |
Absolute indexed mode working properly. All cases were simulated. |
creep |
5620d 18h |
/t6507lp/ |
| 91 |
Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. |
creep |
5620d 19h |
/t6507lp/ |
| 90 |
CMP, CPX and CPY affect carry flag (in this case it indicates a borrow) but they don't affect overflow. |
gabrieloshiro |
5620d 19h |
/t6507lp/ |
| 89 |
Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. |
creep |
5620d 19h |
/t6507lp/ |
| 88 |
Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. |
creep |
5620d 20h |
/t6507lp/ |
| 87 |
Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. |
creep |
5621d 11h |
/t6507lp/ |
| 86 |
Zero page indexed mode is working fine. |
creep |
5621d 15h |
/t6507lp/ |
| 85 |
alu_x and alu_y variables created. |
gabrieloshiro |
5621d 19h |
/t6507lp/ |
| 84 |
X and Y register are passed from ALU to FSM. |
gabrieloshiro |
5621d 19h |
/t6507lp/ |
| 83 |
Completed HAL checking. All the relevant warnings and errors were removed. |
creep |
5621d 20h |
/t6507lp/ |
| 82 |
Did some checking with HAL and fixed 20+ warnings and errors. |
creep |
5622d 12h |
/t6507lp/ |
| 81 |
Decimal mode (BCD) is working. |
gabrieloshiro |
5622d 12h |
/t6507lp/ |
| 80 |
Grouping some instructions that have the same behavioral. |
gabrieloshiro |
5622d 13h |
/t6507lp/ |
| 79 |
ALU testbench added. |
gabrieloshiro |
5622d 14h |
/t6507lp/ |
| 78 |
ZPG coded and simulated. |
creep |
5622d 14h |
/t6507lp/ |
| 77 |
ZPG coded. Simulation is halfway. |
creep |
5622d 15h |
/t6507lp/ |
| 76 |
ABS write instructions were not simulated.
Also added some initial ZPG simulation. |
creep |
5622d 15h |
/t6507lp/ |
| 75 |
First working version! |
gabrieloshiro |
5622d 15h |
/t6507lp/ |
| 74 |
The file now describes who is doing what. |
creep |
5622d 15h |
/t6507lp/ |
| 73 |
Added schedule file into the readme file. |
creep |
5622d 15h |
/t6507lp/ |
| 72 |
Project management folder. |
creep |
5622d 15h |
/t6507lp/ |
| 71 |
Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside. |
creep |
5622d 15h |
/t6507lp/ |
| 70 |
Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased. |
creep |
5626d 12h |
/t6507lp/ |
| 69 |
Added signal origin/destination. |
creep |
5626d 14h |
/t6507lp/ |
| 68 |
The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings. |
creep |
5626d 14h |
/t6507lp/ |
| 67 |
File name change to lowercase. HAL says so! |
creep |
5626d 16h |
/t6507lp/ |
