OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] - Rev 120

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
120 Added some extra commentaries. creep 5621d 17h /t6507lp/trunk/
119 removing old file. creep 5621d 19h /t6507lp/trunk/
118 The top level name was in uppercase. The correct is lowercase. creep 5621d 21h /t6507lp/trunk/
117 Fixed the top level and connected the entire project. creep 5621d 21h /t6507lp/trunk/
116 Changed the module instantiation into the dot form. creep 5621d 21h /t6507lp/trunk/
115 Renamed the signal control. It is mem_rw now. creep 5621d 21h /t6507lp/trunk/
114 Created a global timescale file for the project. Added to the top module. creep 5621d 22h /t6507lp/trunk/
113 Timescale was unified. gabrieloshiro 5621d 22h /t6507lp/trunk/
112 Created a global timescale file for the project. creep 5621d 22h /t6507lp/trunk/
111 Performed some linting after coding was finished. creep 5622d 13h /t6507lp/trunk/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5622d 14h /t6507lp/trunk/
109 PLA and PLP are coded and simulated. creep 5622d 17h /t6507lp/trunk/
108 PHA and PHP are coded and simulated. creep 5622d 18h /t6507lp/trunk/
107 The RTS instruction is working fine. Coded and simulated. creep 5622d 19h /t6507lp/trunk/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5622d 19h /t6507lp/trunk/
105 The RTI instruction is working fine. Coded and simulated. creep 5622d 19h /t6507lp/trunk/
104 The BRK instruction is working. The reset vector was tested also. creep 5622d 21h /t6507lp/trunk/
103 Some early modifications to support the special stack instructions. creep 5623d 14h /t6507lp/trunk/
102 Some early modifications to support the special stack instructions. creep 5623d 17h /t6507lp/trunk/
101 Absolute indirect addressing mode is coded and simulated. creep 5623d 21h /t6507lp/trunk/
100 IDY WRITE TYPE instructions are coded and simulated. creep 5623d 22h /t6507lp/trunk/
99 Only Package.v should be used. creep 5623d 22h /t6507lp/trunk/
98 Updated status and some comments. creep 5623d 22h /t6507lp/trunk/
97 Removed obsolete TODO. creep 5623d 22h /t6507lp/trunk/
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5626d 14h /t6507lp/trunk/
95 IDX addressing mode is also 100%, coded and simulated. creep 5626d 18h /t6507lp/trunk/
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5627d 14h /t6507lp/trunk/
93 Opcode for BNE was wrong. creep 5627d 16h /t6507lp/trunk/
92 Absolute indexed mode working properly. All cases were simulated. creep 5627d 20h /t6507lp/trunk/
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5627d 21h /t6507lp/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.