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[/] [t6507lp/] [trunk/] [rtl/] - Rev 147

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Rev Log message Author Age Path
146 Fixed ticket #13: reset behavior in the FSM. creep 5576d 15h /t6507lp/trunk/rtl/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5576d 17h /t6507lp/trunk/rtl/
144 Checker is working fine. Hunting bugs... creep 5576d 18h /t6507lp/trunk/rtl/
143 Modified the inputs so the alu resets. creep 5576d 19h /t6507lp/trunk/rtl/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5576d 21h /t6507lp/trunk/rtl/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5576d 22h /t6507lp/trunk/rtl/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5576d 22h /t6507lp/trunk/rtl/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5576d 22h /t6507lp/trunk/rtl/
136 Some minor coding style changes. gabrieloshiro 5577d 18h /t6507lp/trunk/rtl/
129 RTL and e files are truly linked now. Some very early coverage is done. creep 5581d 17h /t6507lp/trunk/rtl/
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5581d 21h /t6507lp/trunk/rtl/
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5581d 22h /t6507lp/trunk/rtl/
126 Added a wrapper for the ALU. This file creates the clock for Specman. creep 5581d 22h /t6507lp/trunk/rtl/
120 Added some extra commentaries. creep 5583d 18h /t6507lp/trunk/rtl/
119 removing old file. creep 5583d 20h /t6507lp/trunk/rtl/
118 The top level name was in uppercase. The correct is lowercase. creep 5583d 22h /t6507lp/trunk/rtl/
117 Fixed the top level and connected the entire project. creep 5583d 22h /t6507lp/trunk/rtl/
116 Changed the module instantiation into the dot form. creep 5583d 22h /t6507lp/trunk/rtl/
115 Renamed the signal control. It is mem_rw now. creep 5583d 22h /t6507lp/trunk/rtl/
114 Created a global timescale file for the project. Added to the top module. creep 5583d 23h /t6507lp/trunk/rtl/
113 Timescale was unified. gabrieloshiro 5583d 23h /t6507lp/trunk/rtl/
112 Created a global timescale file for the project. creep 5583d 23h /t6507lp/trunk/rtl/
111 Performed some linting after coding was finished. creep 5584d 14h /t6507lp/trunk/rtl/
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5584d 15h /t6507lp/trunk/rtl/
109 PLA and PLP are coded and simulated. creep 5584d 18h /t6507lp/trunk/rtl/
108 PHA and PHP are coded and simulated. creep 5584d 19h /t6507lp/trunk/rtl/
107 The RTS instruction is working fine. Coded and simulated. creep 5584d 20h /t6507lp/trunk/rtl/
106 First stable version. Things seems to be working. Simulation is currently at 20%. gabrieloshiro 5584d 20h /t6507lp/trunk/rtl/
105 The RTI instruction is working fine. Coded and simulated. creep 5584d 20h /t6507lp/trunk/rtl/
104 The BRK instruction is working. The reset vector was tested also. creep 5584d 22h /t6507lp/trunk/rtl/

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