URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] - Rev 83

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Rev	Log message	Author	Age	Path
83	Completed HAL checking. All the relevant warnings and errors were removed.	creep	5594d 17h	/t6507lp/trunk/rtl/
82	Did some checking with HAL and fixed 20+ warnings and errors.	creep	5595d 10h	/t6507lp/trunk/rtl/
81	Decimal mode (BCD) is working.	gabrieloshiro	5595d 10h	/t6507lp/trunk/rtl/
80	Grouping some instructions that have the same behavioral.	gabrieloshiro	5595d 10h	/t6507lp/trunk/rtl/
79	ALU testbench added.	gabrieloshiro	5595d 11h	/t6507lp/trunk/rtl/
78	ZPG coded and simulated.	creep	5595d 11h	/t6507lp/trunk/rtl/
77	ZPG coded. Simulation is halfway.	creep	5595d 12h	/t6507lp/trunk/rtl/
76	ABS write instructions were not simulated. Also added some initial ZPG simulation.	creep	5595d 12h	/t6507lp/trunk/rtl/
75	First working version!	gabrieloshiro	5595d 12h	/t6507lp/trunk/rtl/
71	Four addressing modes are simulated: immediate, accumulator, implied and absolute. The simulation was done using a testbench that contains a small memory inside.	creep	5595d 13h	/t6507lp/trunk/rtl/
70	Fixed several timing. Registered outputs working. Only three adressing modes coded, the previous coding was erased.	creep	5599d 09h	/t6507lp/trunk/rtl/
68	The FSM module is now parametrized. Also, several changes were made to remove most of the lint warnings.	creep	5599d 12h	/t6507lp/trunk/rtl/
67	File name change to lowercase. HAL says so!	creep	5599d 13h	/t6507lp/trunk/rtl/
66	File name change to lowercase. HAL says so!	creep	5599d 13h	/t6507lp/trunk/rtl/
65	Now the blocks are connected.	gabrieloshiro	5600d 08h	/t6507lp/trunk/rtl/
64	Constant were wrong.	gabrieloshiro	5600d 09h	/t6507lp/trunk/rtl/
63	Fixed several HAL warnings. Still plenty to do.	creep	5600d 09h	/t6507lp/trunk/rtl/
62	The DUT file name changed.	creep	5600d 09h	/t6507lp/trunk/rtl/
61	File name change to lowercase. HAL says so!	creep	5600d 09h	/t6507lp/trunk/rtl/
60	File name change. HAL says so!	creep	5600d 09h	/t6507lp/trunk/rtl/
59	I`ve fixed some latch creation.	gabrieloshiro	5600d 09h	/t6507lp/trunk/rtl/
58	ALU with all opcodes ready for simulation.	gabrieloshiro	5600d 10h	/t6507lp/trunk/rtl/
57	A very simple testbench that checks the execution for a single instruction, i.e. no memory.	creep	5600d 10h	/t6507lp/trunk/rtl/
56	Several changes in the output logic to respect the pipelining.	creep	5600d 10h	/t6507lp/trunk/rtl/
55	ALU has all opcodes now! Comments inside ALU are completely wrong.	gabrieloshiro	5600d 11h	/t6507lp/trunk/rtl/
54	Processor Status register modified.	gabrieloshiro	5600d 14h	/t6507lp/trunk/rtl/
53	Added default header.	creep	5600d 18h	/t6507lp/trunk/rtl/
52	Removed unecessary always block.	creep	5601d 09h	/t6507lp/trunk/rtl/
51	Some first ideas on testbench.	creep	5601d 09h	/t6507lp/trunk/rtl/
48	Updated reference to header file.	creep	5601d 12h	/t6507lp/trunk/rtl/

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] - Rev 83

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