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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 172

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Rev Log message Author Age Path
172 RTI supported to be compatible with stella gabrieloshiro 5574d 15h /t6507lp/trunk/rtl/verilog/
171 Removed debug messages. creep 5574d 16h /t6507lp/trunk/rtl/verilog/
169 ADC bugs finally fixed. gabrieloshiro 5575d 08h /t6507lp/trunk/rtl/verilog/
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5575d 10h /t6507lp/trunk/rtl/verilog/
167 Now SBC is supposed to work. gabrieloshiro 5575d 10h /t6507lp/trunk/rtl/verilog/
166 Commiting again! gabrieloshiro 5575d 10h /t6507lp/trunk/rtl/verilog/
165 SBC and PHP fixed! gabrieloshiro 5575d 10h /t6507lp/trunk/rtl/verilog/
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5575d 12h /t6507lp/trunk/rtl/verilog/
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5575d 13h /t6507lp/trunk/rtl/verilog/
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5575d 13h /t6507lp/trunk/rtl/verilog/
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5575d 13h /t6507lp/trunk/rtl/verilog/
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5578d 10h /t6507lp/trunk/rtl/verilog/
157 gabrieloshiro 5578d 10h /t6507lp/trunk/rtl/verilog/
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5578d 12h /t6507lp/trunk/rtl/verilog/
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5578d 16h /t6507lp/trunk/rtl/verilog/
153 Added a few more instructions to the checker. Removed prints to speed up Specman. creep 5579d 10h /t6507lp/trunk/rtl/verilog/
152 Bug #24 from trac was fixed. gabrieloshiro 5579d 10h /t6507lp/trunk/rtl/verilog/
151 tah comitado! gabrieloshiro 5579d 11h /t6507lp/trunk/rtl/verilog/
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5579d 11h /t6507lp/trunk/rtl/verilog/
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5579d 12h /t6507lp/trunk/rtl/verilog/
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5579d 12h /t6507lp/trunk/rtl/verilog/
146 Fixed ticket #13: reset behavior in the FSM. creep 5580d 09h /t6507lp/trunk/rtl/verilog/
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5580d 11h /t6507lp/trunk/rtl/verilog/
144 Checker is working fine. Hunting bugs... creep 5580d 11h /t6507lp/trunk/rtl/verilog/
143 Modified the inputs so the alu resets. creep 5580d 12h /t6507lp/trunk/rtl/verilog/
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5580d 15h /t6507lp/trunk/rtl/verilog/
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5580d 15h /t6507lp/trunk/rtl/verilog/
140 Variable names were changed according to coding guidelines. gabrieloshiro 5580d 15h /t6507lp/trunk/rtl/verilog/
139 t6507lp_package.v was renamed to avoid uppercase. creep 5580d 15h /t6507lp/trunk/rtl/verilog/
136 Some minor coding style changes. gabrieloshiro 5581d 11h /t6507lp/trunk/rtl/verilog/

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