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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 224

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Rev Log message Author Age Path
224 Added a top level for the tests. creep 5558d 10h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5558d 11h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5558d 13h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5558d 16h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 5559d 11h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 5562d 09h /t6507lp/trunk/rtl/verilog/
218 Added the video converter. creep 5562d 10h /t6507lp/trunk/rtl/verilog/
217 All write operations at the TIA are coded. creep 5563d 16h /t6507lp/trunk/rtl/verilog/
216 Register bank at TIA properly set. Working on the R/W instructions. creep 5564d 12h /t6507lp/trunk/rtl/verilog/
215 Adding the video module. creep 5565d 12h /t6507lp/trunk/rtl/verilog/
214 Added the keyboard controller to the 2600.v top level file. creep 5565d 16h /t6507lp/trunk/rtl/verilog/
212 Bug #56: ZPX page crossing. creep 5570d 17h /t6507lp/trunk/rtl/verilog/
211 Added the keyboard controller testbench to the repository creep 5570d 17h /t6507lp/trunk/rtl/verilog/
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5573d 10h /t6507lp/trunk/rtl/verilog/
204 Finished coding the RIOT. creep 5573d 12h /t6507lp/trunk/rtl/verilog/
203 Adding the RIOT testbench creep 5573d 16h /t6507lp/trunk/rtl/verilog/
202 Bug #49: RTI and RTS behavior was recoded. creep 5576d 09h /t6507lp/trunk/rtl/verilog/
201 Linted the RIOT file. creep 5576d 11h /t6507lp/trunk/rtl/verilog/
200 Bug #48: SP wrong after decrement. creep 5576d 13h /t6507lp/trunk/rtl/verilog/
199 Fixed two warning messages at the FSM. creep 5576d 13h /t6507lp/trunk/rtl/verilog/
198 Removed the old I/O file creep 5576d 16h /t6507lp/trunk/rtl/verilog/
197 Adeed the three modules (io, ram, timer). creep 5576d 16h /t6507lp/trunk/rtl/verilog/
196 Syncing both repositories. creep 5577d 09h /t6507lp/trunk/rtl/verilog/
195 FSM was locking on TSX/TXS. creep 5577d 13h /t6507lp/trunk/rtl/verilog/
194 Fixing bug #45 creep 5577d 15h /t6507lp/trunk/rtl/verilog/
193 Added the io module at the RIOT. creep 5578d 11h /t6507lp/trunk/rtl/verilog/
192 Added the RIOT top level. creep 5578d 12h /t6507lp/trunk/rtl/verilog/
191 Added the testbench for the bus controller. creep 5583d 16h /t6507lp/trunk/rtl/verilog/
190 Bus controller is now linted. creep 5583d 16h /t6507lp/trunk/rtl/verilog/
189 Added the bus controller module. creep 5584d 09h /t6507lp/trunk/rtl/verilog/

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