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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 62

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Rev Log message Author Age Path
62 The DUT file name changed. creep 5634d 17h /t6507lp/trunk/rtl/verilog/
61 File name change to lowercase. HAL says so! creep 5634d 18h /t6507lp/trunk/rtl/verilog/
60 File name change. HAL says so! creep 5634d 18h /t6507lp/trunk/rtl/verilog/
59 I`ve fixed some latch creation. gabrieloshiro 5634d 18h /t6507lp/trunk/rtl/verilog/
58 ALU with all opcodes ready for simulation. gabrieloshiro 5634d 18h /t6507lp/trunk/rtl/verilog/
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5634d 19h /t6507lp/trunk/rtl/verilog/
56 Several changes in the output logic to respect the pipelining. creep 5634d 19h /t6507lp/trunk/rtl/verilog/
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5634d 20h /t6507lp/trunk/rtl/verilog/
54 Processor Status register modified. gabrieloshiro 5634d 22h /t6507lp/trunk/rtl/verilog/
53 Added default header. creep 5635d 03h /t6507lp/trunk/rtl/verilog/
52 Removed unecessary always block. creep 5635d 18h /t6507lp/trunk/rtl/verilog/
51 Some first ideas on testbench. creep 5635d 18h /t6507lp/trunk/rtl/verilog/
48 Updated reference to header file. creep 5635d 20h /t6507lp/trunk/rtl/verilog/
47 Added a new folder where the users should run the tools. creep 5635d 20h /t6507lp/trunk/rtl/verilog/
45 Removed the CVS $log tag. creep 5635d 21h /t6507lp/trunk/rtl/verilog/
44 Now it is compiling using ncvlog. creep 5635d 21h /t6507lp/trunk/rtl/verilog/
38 root 5636d 20h /t6507lp/trunk/rtl/verilog/
37 Some minor fixes. Now we are trying to make it synthesizable. gabrieloshiro 5637d 17h /t6507lp/trunk/rtl/verilog/
36 All module names are written using uppercase letters now. gabrieloshiro 5637d 17h /t6507lp/trunk/rtl/verilog/
35 Several wires created to help code readibility. creep 5637d 18h /t6507lp/trunk/rtl/verilog/
34 Fixed state names. creep 5637d 19h /t6507lp/trunk/rtl/verilog/
33 Some portion of the absolute indexed mode is done, yet is fully nonfunctional. creep 5637d 20h /t6507lp/trunk/rtl/verilog/
32 Documentation is wrong. I`ve just kept the standard. Some ALU operations are not working 100%. Most of them don`t affect Processor Status Register yet. However the main body will be like this. :D gabrieloshiro 5637d 20h /t6507lp/trunk/rtl/verilog/
31 Added zero page indexed mode. creep 5637d 21h /t6507lp/trunk/rtl/verilog/
30 Added zero page mode. creep 5637d 21h /t6507lp/trunk/rtl/verilog/
29 Absolute addressing mode should be working. creep 5637d 22h /t6507lp/trunk/rtl/verilog/
28 More documentation. gabrieloshiro 5637d 23h /t6507lp/trunk/rtl/verilog/
27 Added the pipelining support for a few addressing modes. Still working on absolute addressing mode. creep 5637d 23h /t6507lp/trunk/rtl/verilog/
26 I`m still finishing the documentation. But the file should work by now. gabrieloshiro 5640d 16h /t6507lp/trunk/rtl/verilog/
25 Package file contains all important constants and local parameters. It assigns constant values for opcodes aliases, processor status register indexes, and addressing modes. It is going to help people to understand the code. T65 project has a lot of constants inside its codes. So it is hard to understand it. gabrieloshiro 5640d 18h /t6507lp/trunk/rtl/verilog/

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