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URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] - Rev 47

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Rev Log message Author Age Path
47 New directory structure. root 5566d 07h /t80/trunk/rtl/
46 Made some bugfixes andreas 6854d 00h /trunk/rtl/
45 Fixed loopback break generation jesus 7855d 02h /trunk/rtl/
44 Added some missing features and fixed baud rate generator jesus 7855d 16h /trunk/rtl/
42 Fixed bus req/ack cycle jesus 7864d 03h /trunk/rtl/
41 Removed UNISIM library jesus 7864d 03h /trunk/rtl/
40 Cleanup jesus 7864d 03h /trunk/rtl/
37 Changed to single register file jesus 7892d 04h /trunk/rtl/
36 Added component declaration jesus 7892d 04h /trunk/rtl/
35 Release 0242 jesus 7898d 15h /trunk/rtl/
34 Updated for ISE 5.1 jesus 7898d 21h /trunk/rtl/
29 Fixed (IX/IY+d) timing and added all GB op-codes jesus 7917d 14h /trunk/rtl/
27 Xilinx SSRAM, initial release jesus 7918d 15h /trunk/rtl/
26 Fixed instruction timing for POP and DJNZ jesus 7932d 06h /trunk/rtl/
25 IX/IY timing and ADC/SBC fix jesus 7933d 16h /trunk/rtl/
24 no message jesus 7939d 13h /trunk/rtl/
23 Fixed T2Write jesus 7939d 13h /trunk/rtl/
22 Added 8080 top level jesus 7939d 13h /trunk/rtl/
20 Updated for new T80s generic jesus 7944d 12h /trunk/rtl/
19 Initial version jesus 7944d 12h /trunk/rtl/
18 Added T2Write generic jesus 7944d 19h /trunk/rtl/
17 Removed write through jesus 7946d 11h /trunk/rtl/
16 no message jesus 7946d 15h /trunk/rtl/
15 Added clock enable and fixed IM 2 jesus 7953d 14h /trunk/rtl/
12 Initial import jesus 7973d 03h /trunk/rtl/
11 Added support for XST jesus 7973d 03h /trunk/rtl/
9 Initial import jesus 7974d 14h /trunk/rtl/
8 Fixed refresh address and DJNZ instruction jesus 7974d 15h /trunk/rtl/
7 Initial import jesus 7974d 16h /trunk/rtl/
2 Initial import jesus 8070d 06h /trunk/rtl/

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