| Rev |
Log message |
Author |
Age |
Path |
| 41 |
Well, finally got ports to work properly without latches. Had to reimplement a specific more complex form of RAM basically. The code is horrid, but testcases pass |
earlz |
4420d 12h |
/tinycpu/trunk/src/ |
| 40 |
Design doesn't pass synthesis right now. Not for sure why.
Fixed bug with encoding of second opcode byte in assembler
Added testcase for toggle program |
earlz |
4422d 12h |
/tinycpu/trunk/src/ |
| 39 |
A lot of work in the assembler. It now supports nearly every opcode implemented and is a lot cleaner
Added a bootrom. There isn't really a point in testbenching this.. I'm not for sure how I would, and it will change so much in these early days that it'll be pointless I think
Everything should be ready to go for a test on actual hardware now! |
earlz |
4423d 11h |
/tinycpu/trunk/src/ |
| 38 |
Made it synthesize without latches |
earlz |
4423d 14h |
/tinycpu/trunk/src/ |
| 37 |
Worked on the assembler more
Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some |
earlz |
4425d 12h |
/tinycpu/trunk/src/ |
| 34 |
Implemented load and store instructions (`mov reg, [reg]` and `mov [reg], reg` respectively) |
earlz |
4426d 13h |
/tinycpu/trunk/src/ |
| 33 |
Added more test cases for push/pop. More are still needed though
Fixed SP increment/decrementing
Added new opcode `mov reg,reg` so debugging isn't such a pain |
earlz |
4426d 16h |
/tinycpu/trunk/src/ |
| 32 |
Finished up changes needed to make memory reading actually work.
Push and Pop now work |
earlz |
4426d 18h |
/tinycpu/trunk/src/ |
| 31 |
Removed the infamous TRData latch from ALU. Now synthesizes (sorta) warning free. No latches are used. |
earlz |
4427d 13h |
/tinycpu/trunk/src/ |
| 30 |
After a long weekend of thinking how to do this.. I've decided instead to not strive for a single-cycle computer.
Now, instead, ALU operations will be 2 cycle along with memory operations, and data movement operations are still 1 cycle |
earlz |
4427d 13h |
/tinycpu/trunk/src/ |
| 29 |
Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad. |
earlz |
4430d 20h |
/tinycpu/trunk/src/ |
| 28 |
Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers |
earlz |
4431d 15h |
/tinycpu/trunk/src/ |
| 27 |
Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later |
earlz |
4431d 21h |
/tinycpu/trunk/src/ |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4432d 02h |
/tinycpu/trunk/src/ |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4432d 19h |
/tinycpu/trunk/src/ |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4432d 20h |
/tinycpu/trunk/src/ |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4433d 12h |
/tinycpu/trunk/src/ |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4433d 12h |
/tinycpu/trunk/src/ |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4434d 12h |
/tinycpu/trunk/src/ |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4434d 13h |
/tinycpu/trunk/src/ |
| 18 |
Finished memory controller |
earlz |
4437d 23h |
/tinycpu/trunk/src/ |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4438d 12h |
/tinycpu/trunk/src/ |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4441d 15h |
/tinycpu/trunk/src/ |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4443d 12h |
/tinycpu/trunk/src/ |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4443d 20h |
/tinycpu/trunk/src/ |
| 13 |
Forgot about the new library I added |
earlz |
4443d 23h |
/tinycpu/trunk/src/ |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4444d 00h |
/tinycpu/trunk/src/ |
| 11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4447d 13h |
/tinycpu/trunk/src/ |
| 10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4447d 13h |
/tinycpu/trunk/src/ |
| 9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4447d 21h |
/tinycpu/trunk/src/ |
