OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] - Rev 109

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 Removed mreq_n from cfgo_driver, disconnected interrupt line ghutchis 4863d 13h /tv80/
108 Added environment parameter to control run time ghutchis 4863d 13h /tv80/
107 Fixed memory contention between config interface and TV80 during write ghutchis 4863d 22h /tv80/
106 Additional environment updates. Added sample source code for
application. Fixed memory overflow bug in load_ihex().
ghutchis 4863d 22h /tv80/
105 Fixed bugs after environment bringup ghutchis 4863d 23h /tv80/
104 Added basic SystemC environment for testing sample app ghutchis 4863d 23h /tv80/
103 Updated RTL syntax errors ghutchis 4864d 05h /tv80/
102 Added environment directory for "localcfg" sample app ghutchis 4864d 08h /tv80/
101 Added sample application for local config processor ghutchis 4864d 11h /tv80/
100 Changed do to dout in tv80n, checked in fix for flags bug ghutchis 4895d 10h /tv80/
99 Fixed setting of flags for LD A, I and LD A, R instructions

Added new testcase ivec_flags to cover new opcodes
ghutchis 4953d 07h /tv80/
98 Changed malloc for strings with constant length copy, add assertion checks for
null pointers in env memory, and fixed some formatting
ghutchis 5298d 00h /tv80/
97 Added data in mux, added 16450 UART to environment ghutchis 5302d 03h /tv80/
96 Added Z80 op decode to environment, enabled by -k switch ghutchis 5302d 09h /tv80/
95 Updated regression script to use SystemC simulation ghutchis 5304d 04h /tv80/
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.
ghutchis 5306d 05h /tv80/
93 Added common header file for all systemc environment ghutchis 5307d 04h /tv80/
92 Added responder to top level, beginning of support for ihex load ghutchis 5311d 05h /tv80/
91 Preliminary support for SystemC/Verilator environment ghutchis 5311d 07h /tv80/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5311d 07h /tv80/
89 RTL and environment fixes for nmi bug ghutchis 5331d 10h /tv80/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5333d 01h /tv80/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5348d 08h /tv80/
86 Added old uploaded documents to new repository. root 5571d 14h /tv80/
85 Added old uploaded documents to new repository. root 5571d 20h /tv80/
84 New directory structure. root 5571d 20h /tv80/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.