OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [tags/] [rel_1_0/] - Rev 43

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
43 Fixed assembly routines for blk mem copy test ghutchis 7185d 11h /tv80/tags/rel_1_0/
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define
ghutchis 7185d 11h /tv80/tags/rel_1_0/
41 Added random-read value port ghutchis 7187d 15h /tv80/tags/rel_1_0/
40 Added random-read port and block memory instruction test ghutchis 7187d 15h /tv80/tags/rel_1_0/
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7187d 17h /tv80/tags/rel_1_0/
38 Added command-line options for help (-h) and run with instruction decode (-d) ghutchis 7189d 09h /tv80/tags/rel_1_0/
37 Added new I/O registers for testing block I/O ghutchis 7189d 09h /tv80/tags/rel_1_0/
36 Removed default instruction decode ghutchis 7189d 09h /tv80/tags/rel_1_0/
35 Updated IO registers to add checksum and increment-on-read registers
used for testing block I/O instructions.
ghutchis 7189d 20h /tv80/tags/rel_1_0/
34 Created test for block I/O instructions ghutchis 7189d 20h /tv80/tags/rel_1_0/
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7190d 17h /tv80/tags/rel_1_0/
32 Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1. ghutchis 7205d 20h /tv80/tags/rel_1_0/
31 1) Added environment support for Z80 op decode in log file.
2) Fixed env support for interrupt generation and clearing
ghutchis 7205d 20h /tv80/tags/rel_1_0/
30 Added HTML version of docs ghutchis 7208d 19h /tv80/tags/rel_1_0/
29 Added references ghutchis 7208d 19h /tv80/tags/rel_1_0/
28 Added code to initialize RAM to all 00 at environment start-up time. ghutchis 7208d 20h /tv80/tags/rel_1_0/
27 Modified tvs80 test to run from a ROM image, and work with the
standard environment.
ghutchis 7208d 20h /tv80/tags/rel_1_0/
26 Updated docs ghutchis 7208d 20h /tv80/tags/rel_1_0/
25 Added XML master document ghutchis 7208d 22h /tv80/tags/rel_1_0/
24 tv80s.v ghutchis 7219d 09h /tv80/tags/rel_1_0/
23 Completed conversion to one-hot encoding ghutchis 7231d 23h /tv80/tags/rel_1_0/
22 Changed starting state for one-hot tstate ghutchis 7231d 23h /tv80/tags/rel_1_0/
21 Replaced encoded states with one-hot ghutchis 7233d 00h /tv80/tags/rel_1_0/
5 Added license info headers to all files. Added run2, which splits file
output into a ROM region and a RAM region.
ghutchis 7287d 00h /tv80/tags/rel_1_0/
4 Removed obsolete top level ghutchis 7360d 21h /tv80/tags/rel_1_0/
2 Initial commit ghutchis 7361d 00h /tv80/tags/rel_1_0/
1 Standard project directories initialized by cvs2svn. 7361d 00h /tv80/tags/rel_1_0/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.