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[/] [tv80/] [tags/] [rel_1_0/] - Rev 74

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Rev Log message Author Age Path
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6966d 23h /tv80/tags/rel_1_0/
73 Added RC4 encrypt/decrypt test ghutchis 6978d 18h /tv80/tags/rel_1_0/
72 Added copyright header ghutchis 6978d 18h /tv80/tags/rel_1_0/
71 Ported UART from T80 ghutchis 7039d 21h /tv80/tags/rel_1_0/
70 Added test for T16450 UART ghutchis 7090d 16h /tv80/tags/rel_1_0/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7090d 16h /tv80/tags/rel_1_0/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7098d 17h /tv80/tags/rel_1_0/
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.		 ghutchis 7098d 17h /tv80/tags/rel_1_0/
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7098d 17h /tv80/tags/rel_1_0/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic		 ghutchis 7098d 17h /tv80/tags/rel_1_0/
64 Created rgen script and expanded available register types ghutchis 7099d 16h /tv80/tags/rel_1_0/
63 Added simple regression script. -r command runs all tests (serially),
-c command checks results after all tests have completed.		 ghutchis 7133d 20h /tv80/tags/rel_1_0/
62 Reset timeout counter whenever a message is printed ghutchis 7133d 20h /tv80/tags/rel_1_0/
61 Added timeout disable for large buf sizes ghutchis 7133d 20h /tv80/tags/rel_1_0/
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.		 ghutchis 7133d 21h /tv80/tags/rel_1_0/
59 Added lib for generating MPU interfaces ghutchis 7133d 21h /tv80/tags/rel_1_0/
58 Made TX path async
Made TX clock input instead of output		 ghutchis 7173d 08h /tv80/tags/rel_1_0/
57 Optimized read-back of data using INIR instruction ghutchis 7173d 15h /tv80/tags/rel_1_0/
56 Updated env for simple_gmii with async clk ghutchis 7173d 15h /tv80/tags/rel_1_0/
55 Added documentation of core area and the simple GMII interface block. ghutchis 7173d 17h /tv80/tags/rel_1_0/
54 Test program for network interface ghutchis 7175d 14h /tv80/tags/rel_1_0/
53 Added environment hooks for using and testing the GMII interface ghutchis 7175d 14h /tv80/tags/rel_1_0/
52 Added simple GMII-like interface for testing ghutchis 7175d 14h /tv80/tags/rel_1_0/
45 Added negedge version of top ghutchis 7190d 18h /tv80/tags/rel_1_0/
44 Updated run script for better dump control ghutchis 7190d 20h /tv80/tags/rel_1_0/
43 Fixed assembly routines for blk mem copy test ghutchis 7213d 09h /tv80/tags/rel_1_0/
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define		 ghutchis 7213d 09h /tv80/tags/rel_1_0/
41 Added random-read value port ghutchis 7215d 13h /tv80/tags/rel_1_0/
40 Added random-read port and block memory instruction test ghutchis 7215d 13h /tv80/tags/rel_1_0/
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7215d 15h /tv80/tags/rel_1_0/

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