URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] - Rev 84

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Rev	Log message	Author	Age	Path
84	New directory structure.	root	5569d 00h	/tv80/trunk/
83	Some fixes from Guy-- replace case with casex.	hharte	5642d 06h	/trunk/
82	Clean up spacing	hharte	5652d 02h	/trunk/
81	Initial version of TV80 Wishbone Wrapper	hharte	5652d 03h	/trunk/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6751d 15h	/trunk/
79	Added JR self-checking test	ghutchis	6751d 15h	/trunk/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6794d 17h	/trunk/
77	Added back files lost after server crash	ghutchis	6826d 11h	/trunk/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6905d 17h	/trunk/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6905d 18h	/trunk/
73	Added RC4 encrypt/decrypt test	ghutchis	6917d 12h	/trunk/
72	Added copyright header	ghutchis	6917d 12h	/trunk/
71	Ported UART from T80	ghutchis	6978d 16h	/trunk/
70	Added test for T16450 UART	ghutchis	7029d 11h	/trunk/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7029d 11h	/trunk/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7037d 12h	/trunk/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7037d 12h	/trunk/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7037d 12h	/trunk/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7037d 12h	/trunk/
64	Created rgen script and expanded available register types	ghutchis	7038d 10h	/trunk/
63	Added simple regression script. -r command runs all tests (serially), -c command checks results after all tests have completed.	ghutchis	7072d 15h	/trunk/
62	Reset timeout counter whenever a message is printed	ghutchis	7072d 15h	/trunk/
61	Added timeout disable for large buf sizes	ghutchis	7072d 15h	/trunk/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7072d 15h	/trunk/
59	Added lib for generating MPU interfaces	ghutchis	7072d 15h	/trunk/
58	Made TX path async Made TX clock input instead of output	ghutchis	7112d 03h	/trunk/
57	Optimized read-back of data using INIR instruction	ghutchis	7112d 10h	/trunk/
56	Updated env for simple_gmii with async clk	ghutchis	7112d 10h	/trunk/
55	Added documentation of core area and the simple GMII interface block.	ghutchis	7112d 12h	/trunk/
54	Test program for network interface	ghutchis	7114d 09h	/trunk/

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[/] [tv80/] [trunk/] - Rev 84

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