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[/] [tv80/] [trunk/] - Rev 97

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Rev Log message Author Age Path
97 Added data in mux, added 16450 UART to environment ghutchis 5306d 06h /tv80/trunk/
96 Added Z80 op decode to environment, enabled by -k switch ghutchis 5306d 12h /tv80/trunk/
95 Updated regression script to use SystemC simulation ghutchis 5308d 07h /tv80/trunk/
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.
ghutchis 5310d 08h /tv80/trunk/
93 Added common header file for all systemc environment ghutchis 5311d 06h /tv80/trunk/
92 Added responder to top level, beginning of support for ihex load ghutchis 5315d 08h /tv80/trunk/
91 Preliminary support for SystemC/Verilator environment ghutchis 5315d 10h /tv80/trunk/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5315d 10h /tv80/trunk/
89 RTL and environment fixes for nmi bug ghutchis 5335d 13h /tv80/trunk/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5337d 04h /tv80/trunk/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5352d 11h /tv80/trunk/
84 New directory structure. root 5575d 23h /tv80/trunk/
83 Some fixes from Guy-- replace case with casex. hharte 5649d 05h /trunk/
82 Clean up spacing hharte 5659d 01h /trunk/
81 Initial version of TV80 Wishbone Wrapper hharte 5659d 02h /trunk/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6758d 14h /trunk/
79 Added JR self-checking test ghutchis 6758d 14h /trunk/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6801d 15h /trunk/
77 Added back files lost after server crash ghutchis 6833d 09h /trunk/
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.
ghutchis 6912d 15h /trunk/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6912d 16h /trunk/
73 Added RC4 encrypt/decrypt test ghutchis 6924d 11h /trunk/
72 Added copyright header ghutchis 6924d 11h /trunk/
71 Ported UART from T80 ghutchis 6985d 15h /trunk/
70 Added test for T16450 UART ghutchis 7036d 10h /trunk/
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7036d 10h /trunk/
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.
ghutchis 7044d 11h /trunk/
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7044d 11h /trunk/
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7044d 11h /trunk/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic
ghutchis 7044d 11h /trunk/

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