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[/] [tv80/] [trunk/] [rtl/] - Rev 109

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Rev Log message Author Age Path
109 Removed mreq_n from cfgo_driver, disconnected interrupt line ghutchis 4868d 04h /tv80/trunk/rtl/
107 Fixed memory contention between config interface and TV80 during write ghutchis 4868d 14h /tv80/trunk/rtl/
105 Fixed bugs after environment bringup ghutchis 4868d 15h /tv80/trunk/rtl/
103 Updated RTL syntax errors ghutchis 4868d 21h /tv80/trunk/rtl/
101 Added sample application for local config processor ghutchis 4869d 03h /tv80/trunk/rtl/
100 Changed do to dout in tv80n, checked in fix for flags bug ghutchis 4900d 01h /tv80/trunk/rtl/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5315d 22h /tv80/trunk/rtl/
89 RTL and environment fixes for nmi bug ghutchis 5336d 01h /tv80/trunk/rtl/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5337d 16h /tv80/trunk/rtl/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5353d 00h /tv80/trunk/rtl/
84 New directory structure. root 5576d 12h /tv80/trunk/rtl/
83 Some fixes from Guy-- replace case with casex. hharte 5649d 18h /trunk/rtl/
82 Clean up spacing hharte 5659d 14h /trunk/rtl/
81 Initial version of TV80 Wishbone Wrapper hharte 5659d 14h /trunk/rtl/
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6759d 02h /trunk/rtl/
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6802d 04h /trunk/rtl/
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6913d 05h /trunk/rtl/
71 Ported UART from T80 ghutchis 6986d 04h /trunk/rtl/
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic
ghutchis 7044d 23h /trunk/rtl/
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.
ghutchis 7080d 03h /trunk/rtl/
58 Made TX path async
Made TX clock input instead of output
ghutchis 7119d 14h /trunk/rtl/
52 Added simple GMII-like interface for testing ghutchis 7121d 20h /trunk/rtl/
45 Added negedge version of top ghutchis 7137d 00h /trunk/rtl/
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7164d 21h /trunk/rtl/
24 tv80s.v ghutchis 7193d 14h /trunk/rtl/
23 Completed conversion to one-hot encoding ghutchis 7206d 04h /trunk/rtl/
22 Changed starting state for one-hot tstate ghutchis 7206d 04h /trunk/rtl/
21 Replaced encoded states with one-hot ghutchis 7207d 04h /trunk/rtl/
4 Removed obsolete top level ghutchis 7335d 01h /trunk/rtl/
2 Initial commit ghutchis 7335d 04h /trunk/rtl/

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