OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [asyst_2/] [rtl/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5570d 23h /uart16550/tags/asyst_2/rtl/
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8146d 16h /uart16550/tags/asyst_2/rtl/
75 Endian define added. Big Byte Endian is selected by default. mohor 8146d 16h /uart16550/tags/asyst_2/rtl/
74 tf_overrun signal was disabled since it was not used gorban 8151d 18h /uart16550/tags/asyst_2/rtl/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8158d 17h /uart16550/tags/asyst_2/rtl/
71 Removed confusing comment gorban 8183d 13h /uart16550/tags/asyst_2/rtl/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8188d 22h /uart16550/tags/asyst_2/rtl/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8197d 13h /uart16550/tags/asyst_2/rtl/
68 lsr[7] was not showing overrun errors. mohor 8200d 20h /uart16550/tags/asyst_2/rtl/
67 Missing declaration of rf_push_q fixed. mohor 8207d 20h /uart16550/tags/asyst_2/rtl/
66 rx push changed to be only one cycle wide. mohor 8207d 20h /uart16550/tags/asyst_2/rtl/
65 Warnings fixed (unused signals removed). mohor 8209d 01h /uart16550/tags/asyst_2/rtl/
64 Warnings cleared. mohor 8209d 01h /uart16550/tags/asyst_2/rtl/
63 Synplicity was having troubles with the comment. mohor 8209d 02h /uart16550/tags/asyst_2/rtl/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8210d 00h /uart16550/tags/asyst_2/rtl/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8210d 19h /uart16550/tags/asyst_2/rtl/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8210d 23h /uart16550/tags/asyst_2/rtl/
59 MSR register fixed. mohor 8213d 20h /uart16550/tags/asyst_2/rtl/
58 After reset modem status register MSR should be reset. mohor 8213d 23h /uart16550/tags/asyst_2/rtl/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8214d 23h /uart16550/tags/asyst_2/rtl/
56 thre irq should be cleared only when being source of interrupt. mohor 8214d 23h /uart16550/tags/asyst_2/rtl/
55 some synthesis bugs fixed gorban 8215d 11h /uart16550/tags/asyst_2/rtl/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8216d 00h /uart16550/tags/asyst_2/rtl/
53 Scratch register define added. mohor 8217d 00h /uart16550/tags/asyst_2/rtl/
52 Scratch register added gorban 8217d 14h /uart16550/tags/asyst_2/rtl/
51 Igor fixed break condition bugs gorban 8217d 14h /uart16550/tags/asyst_2/rtl/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8221d 19h /uart16550/tags/asyst_2/rtl/
49 committed the debug interface file gorban 8223d 12h /uart16550/tags/asyst_2/rtl/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8224d 12h /uart16550/tags/asyst_2/rtl/
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8229d 14h /uart16550/tags/asyst_2/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.