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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 57

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Rev Log message Author Age Path
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8274d 05h /uart16550/tags/asyst_3/rtl/verilog/
56 thre irq should be cleared only when being source of interrupt. mohor 8274d 05h /uart16550/tags/asyst_3/rtl/verilog/
55 some synthesis bugs fixed gorban 8274d 17h /uart16550/tags/asyst_3/rtl/verilog/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8275d 06h /uart16550/tags/asyst_3/rtl/verilog/
53 Scratch register define added. mohor 8276d 07h /uart16550/tags/asyst_3/rtl/verilog/
52 Scratch register added gorban 8276d 20h /uart16550/tags/asyst_3/rtl/verilog/
51 Igor fixed break condition bugs gorban 8276d 20h /uart16550/tags/asyst_3/rtl/verilog/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8281d 01h /uart16550/tags/asyst_3/rtl/verilog/
49 committed the debug interface file gorban 8282d 18h /uart16550/tags/asyst_3/rtl/verilog/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8283d 18h /uart16550/tags/asyst_3/rtl/verilog/
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8288d 20h /uart16550/tags/asyst_3/rtl/verilog/
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8289d 17h /uart16550/tags/asyst_3/rtl/verilog/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8290d 18h /uart16550/tags/asyst_3/rtl/verilog/
44 fixed more typo bugs gorban 8304d 18h /uart16550/tags/asyst_3/rtl/verilog/
43 lsr1r error fixed. mohor 8305d 00h /uart16550/tags/asyst_3/rtl/verilog/
42 ti_int_pnd error fixed. mohor 8305d 01h /uart16550/tags/asyst_3/rtl/verilog/
41 ti_int_d error fixed. mohor 8305d 01h /uart16550/tags/asyst_3/rtl/verilog/
40 Synthesis bugs fixed. Some other minor changes gorban 8307d 03h /uart16550/tags/asyst_3/rtl/verilog/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8309d 01h /uart16550/tags/asyst_3/rtl/verilog/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8309d 22h /uart16550/tags/asyst_3/rtl/verilog/
36 no message mohor 8315d 06h /uart16550/tags/asyst_3/rtl/verilog/
35 Fixes to break and timeout conditions gorban 8317d 00h /uart16550/tags/asyst_3/rtl/verilog/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8318d 22h /uart16550/tags/asyst_3/rtl/verilog/
33 Small synopsis fixes gorban 8328d 06h /uart16550/tags/asyst_3/rtl/verilog/
32 Changes data_out to be synchronous again as it should have been. gorban 8328d 23h /uart16550/tags/asyst_3/rtl/verilog/
31 small fix gorban 8329d 19h /uart16550/tags/asyst_3/rtl/verilog/
30 Modified port names again gorban 8384d 00h /uart16550/tags/asyst_3/rtl/verilog/
29 Things connected to parity changed.
Clock devider changed.		 mohor 8384d 18h /uart16550/tags/asyst_3/rtl/verilog/
28 FIFO was not cleared after the data was read bug fixed. mohor 8385d 07h /uart16550/tags/asyst_3/rtl/verilog/
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8385d 23h /uart16550/tags/asyst_3/rtl/verilog/

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