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[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5578d 09h /uart16550/tags/rel_3/rtl/
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7332d 06h /uart16550/tags/rel_3/rtl/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7332d 06h /uart16550/tags/rel_3/rtl/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7332d 07h /uart16550/tags/rel_3/rtl/
99 Added synchronizer flops for RX input. tadejm 7332d 07h /uart16550/tags/rel_3/rtl/
98 Added to synchronize RX input to Wishbone clock. tadejm 7332d 07h /uart16550/tags/rel_3/rtl/
89 adjusted comment + define dries 7584d 12h /uart16550/tags/rel_3/rtl/
88 added clearing the receiver fifo statuses on resets gorban 7647d 01h /uart16550/tags/rel_3/rtl/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7677d 02h /uart16550/tags/rel_3/rtl/
84 The uart_defines.v file is included again in sources. gorban 7993d 22h /uart16550/tags/rel_3/rtl/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 8000d 20h /uart16550/tags/rel_3/rtl/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 8000d 20h /uart16550/tags/rel_3/rtl/
75 Endian define added. Big Byte Endian is selected by default. mohor 8154d 02h /uart16550/tags/rel_3/rtl/
74 tf_overrun signal was disabled since it was not used gorban 8159d 04h /uart16550/tags/rel_3/rtl/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8166d 03h /uart16550/tags/rel_3/rtl/
71 Removed confusing comment gorban 8190d 23h /uart16550/tags/rel_3/rtl/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8196d 08h /uart16550/tags/rel_3/rtl/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8204d 22h /uart16550/tags/rel_3/rtl/
68 lsr[7] was not showing overrun errors. mohor 8208d 06h /uart16550/tags/rel_3/rtl/
67 Missing declaration of rf_push_q fixed. mohor 8215d 06h /uart16550/tags/rel_3/rtl/
66 rx push changed to be only one cycle wide. mohor 8215d 06h /uart16550/tags/rel_3/rtl/
65 Warnings fixed (unused signals removed). mohor 8216d 10h /uart16550/tags/rel_3/rtl/
64 Warnings cleared. mohor 8216d 11h /uart16550/tags/rel_3/rtl/
63 Synplicity was having troubles with the comment. mohor 8216d 11h /uart16550/tags/rel_3/rtl/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8217d 10h /uart16550/tags/rel_3/rtl/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8218d 04h /uart16550/tags/rel_3/rtl/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8218d 09h /uart16550/tags/rel_3/rtl/
59 MSR register fixed. mohor 8221d 06h /uart16550/tags/rel_3/rtl/
58 After reset modem status register MSR should be reset. mohor 8221d 09h /uart16550/tags/rel_3/rtl/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8222d 09h /uart16550/tags/rel_3/rtl/

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