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[/] [uart16550/] [trunk/] - Rev 60

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Rev Log message Author Age Path
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8230d 12h /uart16550/trunk/
59 MSR register fixed. mohor 8233d 09h /uart16550/trunk/
58 After reset modem status register MSR should be reset. mohor 8233d 12h /uart16550/trunk/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8234d 12h /uart16550/trunk/
56 thre irq should be cleared only when being source of interrupt. mohor 8234d 12h /uart16550/trunk/
55 some synthesis bugs fixed gorban 8235d 00h /uart16550/trunk/
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8235d 13h /uart16550/trunk/
53 Scratch register define added. mohor 8236d 13h /uart16550/trunk/
52 Scratch register added gorban 8237d 02h /uart16550/trunk/
51 Igor fixed break condition bugs gorban 8237d 02h /uart16550/trunk/
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8241d 07h /uart16550/trunk/
49 committed the debug interface file gorban 8243d 01h /uart16550/trunk/
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8244d 00h /uart16550/trunk/
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8249d 02h /uart16550/trunk/
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8250d 00h /uart16550/trunk/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8251d 00h /uart16550/trunk/
44 fixed more typo bugs gorban 8265d 00h /uart16550/trunk/
43 lsr1r error fixed. mohor 8265d 07h /uart16550/trunk/
42 ti_int_pnd error fixed. mohor 8265d 07h /uart16550/trunk/
41 ti_int_d error fixed. mohor 8265d 07h /uart16550/trunk/
40 Synthesis bugs fixed. Some other minor changes gorban 8267d 09h /uart16550/trunk/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8269d 07h /uart16550/trunk/
38 small update to test interrupts gorban 8270d 04h /uart16550/trunk/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8270d 04h /uart16550/trunk/
36 no message mohor 8275d 12h /uart16550/trunk/
35 Fixes to break and timeout conditions gorban 8277d 07h /uart16550/trunk/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8279d 05h /uart16550/trunk/
33 Small synopsis fixes gorban 8288d 12h /uart16550/trunk/
32 Changes data_out to be synchronous again as it should have been. gorban 8289d 06h /uart16550/trunk/
31 small fix gorban 8290d 01h /uart16550/trunk/

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