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[/] [uart16550/] [trunk/] - Rev 87

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87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7706d 19h /uart16550/trunk/
86 restored include for uart_defines.v in uart_test.v gorban 7976d 23h /uart16550/trunk/
85 Updated documentation to include latest changes. gorban 8010d 15h /uart16550/trunk/
84 The uart_defines.v file is included again in sources. gorban 8023d 14h /uart16550/trunk/
83 Reverted to include uart_defines.v file in other files again. gorban 8023d 14h /uart16550/trunk/
82 Updated to work with latest core. gorban 8030d 12h /uart16550/trunk/
81 Added lastest additions. gorban 8030d 12h /uart16550/trunk/
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 8030d 12h /uart16550/trunk/
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 8030d 12h /uart16550/trunk/
75 Endian define added. Big Byte Endian is selected by default. mohor 8183d 19h /uart16550/trunk/
74 tf_overrun signal was disabled since it was not used gorban 8188d 20h /uart16550/trunk/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8195d 19h /uart16550/trunk/
72 UART PHY added. Files are fully operational, working on HW. mohor 8209d 03h /uart16550/trunk/
71 Removed confusing comment gorban 8220d 15h /uart16550/trunk/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8226d 00h /uart16550/trunk/
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8234d 15h /uart16550/trunk/
68 lsr[7] was not showing overrun errors. mohor 8237d 22h /uart16550/trunk/
67 Missing declaration of rf_push_q fixed. mohor 8244d 22h /uart16550/trunk/
66 rx push changed to be only one cycle wide. mohor 8244d 22h /uart16550/trunk/
65 Warnings fixed (unused signals removed). mohor 8246d 03h /uart16550/trunk/
64 Warnings cleared. mohor 8246d 03h /uart16550/trunk/
63 Synplicity was having troubles with the comment. mohor 8246d 04h /uart16550/trunk/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8247d 02h /uart16550/trunk/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8247d 21h /uart16550/trunk/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.		 mohor 8248d 01h /uart16550/trunk/
59 MSR register fixed. mohor 8250d 22h /uart16550/trunk/
58 After reset modem status register MSR should be reset. mohor 8251d 01h /uart16550/trunk/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8252d 01h /uart16550/trunk/
56 thre irq should be cleared only when being source of interrupt. mohor 8252d 01h /uart16550/trunk/
55 some synthesis bugs fixed gorban 8252d 13h /uart16550/trunk/

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