OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] - Rev 32

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 Change baud generator to create a overclock frequency of 8x the baud rate....
Change the serial receiver to sample the signal on the middle of the serial input, now it's using only the overclocked baud...
leonardoaraujo.santos 4451d 10h /uart_block/
31 Working on documentation and on Chipscope leonardoaraujo.santos 4451d 22h /uart_block/
30 Preparing to work with chipscope leonardoaraujo.santos 4451d 22h /uart_block/
29 Preparing to work with chipscope leonardoaraujo.santos 4451d 23h /uart_block/
28 Changing wrong datasheet of Spartan3A kit for newer one.... Detected some bug on the reception (When is fast it seems that the reception could be wrong...) leonardoaraujo.santos 4452d 00h /uart_block/
27 First version seems working nice on the PC!!! leonardoaraujo.santos 4452d 00h /uart_block/
26 Adding Spartan3A Starter kit leonardoaraujo.santos 4452d 07h /uart_block/
25 Adding some sample code on the doc folder, also adding the wishbone public domain library file leonardoaraujo.santos 4452d 08h /uart_block/
24 Working on testbench and refactoring... now we could start some tests on the board... leonardoaraujo.santos 4453d 05h /uart_block/
23 Working on uart_control refactoring leonardoaraujo.santos 4453d 06h /uart_block/
22 Refactoring the uart_control leonardoaraujo.santos 4453d 09h /uart_block/
21 Preparing to rewrite uart_control, adding pin to indicate data available at the RX leonardoaraujo.santos 4453d 16h /uart_block/
20 Finishing at least the tests on testbench.... Was good to verify that the uart_control should be redesigned to allow concurrent receive and to clean the code... leonardoaraujo.santos 4454d 00h /uart_block/
19 Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd) leonardoaraujo.santos 4454d 00h /uart_block/
18 sdsd leonardoaraujo.santos 4454d 07h /uart_block/
17 Working on slave testbench and fixing some bugs leonardoaraujo.santos 4454d 08h /uart_block/
16 Adding testbench for wishbone slave module leonardoaraujo.santos 4454d 09h /uart_block/
15 Taking out some warnings and transparent latches from the design leonardoaraujo.santos 4454d 10h /uart_block/
14 Fixing some warnings... Adding wishbone slave leonardoaraujo.santos 4455d 05h /uart_block/
13 Working on uart_control testbench... also applying some fixes... leonardoaraujo.santos 4455d 06h /uart_block/
12 Working on the communication blocks leonardoaraujo.santos 4455d 07h /uart_block/
11 Adding uart_communication_block leonardoaraujo.santos 4455d 10h /uart_block/
10 Working on the control unit part leonardoaraujo.santos 4455d 14h /uart_block/
9 Adding Control unit for uart block leonardoaraujo.santos 4456d 01h /uart_block/
8 Solving some bugs in baud_generator.vhd leonardoaraujo.santos 4456d 12h /uart_block/
7 Remember to clean project files leonardoaraujo.santos 4457d 09h /uart_block/
6 Adding baud generator leonardoaraujo.santos 4457d 09h /uart_block/
5 Adding sequential division (32 cycles per 32 bit word) leonardoaraujo.santos 4462d 10h /uart_block/
4 Working on receiver leonardoaraujo.santos 4464d 11h /uart_block/
3 Deleting unused files and changing tests leonardoaraujo.santos 4464d 11h /uart_block/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.