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[/] [usb_dongle_fpga/] [tags/] [version_1_5/] - Rev 29

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Rev Log message Author Age Path
29 Added link to cheap ($40) ByteBlaster clone cable to update notice and fix'ed help typo nuubik 5953d 09h /usb_dongle_fpga/tags/version_1_5/
28 Quartus project files for HW code 5 project files nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
27 Initial commit of post code logger block and fifo used in the logger nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
26 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added post code logger block and LPC IO write flow control and flash lock when flash is programmed		 nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
25 Added flash_sts status check as flash_sts pin works now (flas_sts had 2 inputs pins what caused it not to work propery now one is highZ output).
Added 64K byte block read when read length is 0		 nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
24 Added changes for new dongle HW code 5 features nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
23 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed.
Forced serial port to hw flow control mode.
Added support for new dongle HW code 5 to support fast read and fast write modes		 nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
22 Inlined dongle spesific Uspp code to dongle.py script separate Uspp is no longer needed nuubik 5954d 10h /usb_dongle_fpga/tags/version_1_5/
20 Fix'ed TAR cycle second part this is not critical update nuubik 5967d 13h /usb_dongle_fpga/tags/version_1_5/
19 Fix'ed cycle type init code copy/pase mistake nuubik 5967d 15h /usb_dongle_fpga/tags/version_1_5/
18 Fixed in reset init of some trigers (this should not have generated extra hardware in FPGA but just to be on the safe side) nuubik 5968d 14h /usb_dongle_fpga/tags/version_1_5/
17 changed version code to 04 and added spy mode by puting jumpers on header and also implemented LPC Firmware Hub read to enable this booting mode (selectable by header jumper see documentation) nuubik 5968d 15h /usb_dongle_fpga/tags/version_1_5/
16 Synchronisation with OpenCores release nuubik 6101d 11h /usb_dongle_fpga/tags/version_1_5/
15 changed version code to 03 and disabled spy mode on juper setting 00 (this disabled booting but postcode IO write was displayed) nuubik 6218d 14h /usb_dongle_fpga/tags/version_1_5/
14 added comment on POR time influence when booting from LPC dongle nuubik 6230d 13h /usb_dongle_fpga/tags/version_1_5/
12 Added windows py bindings check with nice info print with link to installer nuubik 6332d 07h /usb_dongle_fpga/tags/version_1_5/
11 one ; in line end possible runtime error nuubik 6332d 07h /usb_dongle_fpga/tags/version_1_5/
10 fixed a typo nuubik 6336d 05h /usb_dongle_fpga/tags/version_1_5/
9 Made failing on port open retry nuubik 6336d 05h /usb_dongle_fpga/tags/version_1_5/
8 Added PCB level test options nuubik 6336d 12h /usb_dongle_fpga/tags/version_1_5/
7 Fixed pin modes and resyntesized nuubik 6336d 12h /usb_dongle_fpga/tags/version_1_5/
6 Fixed Cyclon part no in datasheets and drawings nuubik 6373d 10h /usb_dongle_fpga/tags/version_1_5/
4 Changed LED SM front to falling to avoid large current switches at the same time as data nuubik 6399d 05h /usb_dongle_fpga/tags/version_1_5/
3 Changed outputs to LVCMOS and lowered drive current to 2mA to avoid noise on longer tracs and fast switching speeds nuubik 6399d 05h /usb_dongle_fpga/tags/version_1_5/
2 Initial global code commit nuubik 6413d 13h /usb_dongle_fpga/tags/version_1_5/
1 Standard project directories initialized by cvs2svn. 6413d 13h /usb_dongle_fpga/tags/version_1_5/

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