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URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] [v586/] - Rev 106

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Rev Log message Author Age Path
106 update core netlist ultro 2939d 10h /v586/
105 migration nexys ddr ultro 2939d 12h /v586/
104 iadd rstgen and clk wiard for ddr nexys4 TOP ultro 2946d 11h /v586/
103 commit top for 128mbyte nexys4 ddr version ultro 2956d 01h /v586/
102 committed 128mbytes boot code for nexys4 ddr ultro 2956d 01h /v586/
101 add ddr interface mig7 xilinx xci ip ultro 2956d 15h /v586/
100 add crossbar for nexys4 ddr with 128megabyte ram window ultro 2956d 15h /v586/
99 remove phy_intn from xdc constraints as it is not used inside design wi th etherlite. ultro 2997d 23h /v586/
98 update tbench and add mii to rmii converter ip from xilinx ultro 2998d 09h /v586/
97 update periph and TOP ultro 2998d 09h /v586/
96 update periph , uart is not inside ultro 2998d 09h /v586/
95 update boot.mem accordingly to test.s cleanup ultro 3000d 12h /v586/
94 clean up test.s ultro 3000d 12h /v586/
93 added stub for keyboard ultro 3001d 01h /v586/
92 added doc ultro 3001d 03h /v586/
91 update netlists cosmetics ultro 3001d 15h /v586/
90 updated cosmetic periph.v ultro 3001d 16h /v586/
89 add 3x rtl files ultro 3001d 17h /v586/
88 remove axi ip standalone ultro 3001d 17h /v586/
87 update rtl for boot.mem ultro 3001d 17h /v586/
86 update tbench ultro 3001d 17h /v586/
85 supress 2 files acu.v and clk_wiz.vhd ultro 3001d 17h /v586/
84 add Xilinx xci ip repo ultro 3001d 18h /v586/
83 cleanup ultro 3001d 19h /v586/
82 delete ucf ultro 3001d 19h /v586/
81 update linux patch instead of config , to generated the kinux kernel ultro 3001d 19h /v586/
80 update TOP_SYS.xdc for sd & gpios ultro 3001d 19h /v586/
79 replaced linux with SD version and root.bon with initramfz.cpio.gz from buildroot 2016.02 with micropython and e2fs utilities ultro 3001d 19h /v586/
78 fix mci ultro 3001d 19h /v586/
77 update mcs files with axi version and buildroot 2016.02 and micropython ultro 3001d 19h /v586/

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