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[/] [versatile_fifo/] [trunk/] - Rev 29

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Rev Log message Author Age Path
29 ACTEL syn define unneback 5041d 20h /versatile_fifo/trunk/
28 ACTEL async dual way FIFO unneback 5049d 06h /versatile_fifo/trunk/
27 initial commit, dual way simplex FIFO unneback 5049d 21h /versatile_fifo/trunk/
26 added ACTEL synthesis directive as define, +ACTEL unneback 5049d 21h /versatile_fifo/trunk/
25 DFF SR as separate logic unneback 5189d 17h /versatile_fifo/trunk/
24 updated fifo interfaces with re/rd and we/wr unneback 5190d 08h /versatile_fifo/trunk/
23 unneback 5192d 20h /versatile_fifo/trunk/
22 async fifo with multiple queues unneback 5192d 21h /versatile_fifo/trunk/
21 added DFF SR unneback 5206d 18h /versatile_fifo/trunk/
20 unneback 5207d 01h /versatile_fifo/trunk/
19 DFF with async clear and set for Altera cycloneIV unneback 5208d 07h /versatile_fifo/trunk/
18 ADDR and DATA width set to 8 resp 32 unneback 5208d 21h /versatile_fifo/trunk/
17 based on updated versatile counter unneback 5212d 20h /versatile_fifo/trunk/
16 changed power of two style unneback 5476d 05h /versatile_fifo/trunk/
15 doc updated
gray_counter_defines added
dual port RAM updated		 unneback 5479d 23h /versatile_fifo/trunk/
14 added PDF unneback 5524d 06h /versatile_fifo/trunk/
13 adr update unneback 5525d 08h /versatile_fifo/trunk/
12 no mux on dual port mem read unneback 5538d 01h /versatile_fifo/trunk/
11 name conflict
wptr1 changed to wptr1_cnt etc		 unneback 5538d 04h /versatile_fifo/trunk/
10 rptr2 unneback 5538d 05h /versatile_fifo/trunk/
9 unneback 5544d 01h /versatile_fifo/trunk/
8 unneback 5544d 01h /versatile_fifo/trunk/
7 unneback 5544d 01h /versatile_fifo/trunk/
6 unneback 5544d 04h /versatile_fifo/trunk/
5 async compare for fifo full and empty unneback 5544d 04h /versatile_fifo/trunk/
4 unneback 5544d 08h /versatile_fifo/trunk/
3 unneback 5544d 08h /versatile_fifo/trunk/
2 unneback 5544d 09h /versatile_fifo/trunk/
1 The project was created and the structure was created root 5546d 03h /versatile_fifo/trunk/

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