URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] - Rev 26

Rev	Log message	Author	Age	Path
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5070d 14h	/versatile_fifo/trunk/rtl/
25	DFF SR as separate logic	unneback	5210d 09h	/versatile_fifo/trunk/rtl/
24	updated fifo interfaces with re/rd and we/wr	unneback	5211d 00h	/versatile_fifo/trunk/rtl/
23		unneback	5213d 12h	/versatile_fifo/trunk/rtl/
22	async fifo with multiple queues	unneback	5213d 13h	/versatile_fifo/trunk/rtl/
21	added DFF SR	unneback	5227d 10h	/versatile_fifo/trunk/rtl/
18	ADDR and DATA width set to 8 resp 32	unneback	5229d 13h	/versatile_fifo/trunk/rtl/
17	based on updated versatile counter	unneback	5233d 12h	/versatile_fifo/trunk/rtl/
16	changed power of two style	unneback	5496d 22h	/versatile_fifo/trunk/rtl/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5500d 15h	/versatile_fifo/trunk/rtl/
13	adr update	unneback	5546d 00h	/versatile_fifo/trunk/rtl/
12	no mux on dual port mem read	unneback	5558d 17h	/versatile_fifo/trunk/rtl/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5558d 20h	/versatile_fifo/trunk/rtl/
10	rptr2	unneback	5558d 21h	/versatile_fifo/trunk/rtl/
9		unneback	5564d 17h	/versatile_fifo/trunk/rtl/
8		unneback	5564d 17h	/versatile_fifo/trunk/rtl/
7		unneback	5564d 17h	/versatile_fifo/trunk/rtl/
6		unneback	5564d 20h	/versatile_fifo/trunk/rtl/
5	async compare for fifo full and empty	unneback	5564d 20h	/versatile_fifo/trunk/rtl/
4		unneback	5565d 00h	/versatile_fifo/trunk/rtl/
2		unneback	5565d 01h	/versatile_fifo/trunk/rtl/