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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 4982d 14h /versatile_fifo/trunk/rtl/verilog/
31 port map unneback 5053d 07h /versatile_fifo/trunk/rtl/verilog/
30 port map unneback 5053d 08h /versatile_fifo/trunk/rtl/verilog/
29 ACTEL syn define unneback 5061d 05h /versatile_fifo/trunk/rtl/verilog/
28 ACTEL async dual way FIFO unneback 5068d 15h /versatile_fifo/trunk/rtl/verilog/
27 initial commit, dual way simplex FIFO unneback 5069d 06h /versatile_fifo/trunk/rtl/verilog/
26 added ACTEL synthesis directive as define, +ACTEL unneback 5069d 06h /versatile_fifo/trunk/rtl/verilog/
25 DFF SR as separate logic unneback 5209d 02h /versatile_fifo/trunk/rtl/verilog/
24 updated fifo interfaces with re/rd and we/wr unneback 5209d 16h /versatile_fifo/trunk/rtl/verilog/
23 unneback 5212d 05h /versatile_fifo/trunk/rtl/verilog/
22 async fifo with multiple queues unneback 5212d 05h /versatile_fifo/trunk/rtl/verilog/
21 added DFF SR unneback 5226d 03h /versatile_fifo/trunk/rtl/verilog/
18 ADDR and DATA width set to 8 resp 32 unneback 5228d 06h /versatile_fifo/trunk/rtl/verilog/
17 based on updated versatile counter unneback 5232d 04h /versatile_fifo/trunk/rtl/verilog/
16 changed power of two style unneback 5495d 14h /versatile_fifo/trunk/rtl/verilog/
15 doc updated
gray_counter_defines added
dual port RAM updated		 unneback 5499d 08h /versatile_fifo/trunk/rtl/verilog/
13 adr update unneback 5544d 16h /versatile_fifo/trunk/rtl/verilog/
12 no mux on dual port mem read unneback 5557d 10h /versatile_fifo/trunk/rtl/verilog/
11 name conflict
wptr1 changed to wptr1_cnt etc		 unneback 5557d 12h /versatile_fifo/trunk/rtl/verilog/
10 rptr2 unneback 5557d 14h /versatile_fifo/trunk/rtl/verilog/
9 unneback 5563d 09h /versatile_fifo/trunk/rtl/verilog/
8 unneback 5563d 09h /versatile_fifo/trunk/rtl/verilog/
7 unneback 5563d 09h /versatile_fifo/trunk/rtl/verilog/
6 unneback 5563d 12h /versatile_fifo/trunk/rtl/verilog/
5 async compare for fifo full and empty unneback 5563d 12h /versatile_fifo/trunk/rtl/verilog/
4 unneback 5563d 16h /versatile_fifo/trunk/rtl/verilog/
2 unneback 5563d 17h /versatile_fifo/trunk/rtl/verilog/

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