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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 44

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Rev Log message Author Age Path
44 added target independet IO functionns unneback 4860d 15h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4864d 18h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 4868d 18h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 4868d 20h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 4868d 20h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 4869d 17h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 4869d 17h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 4875d 13h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 4876d 22h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4877d 09h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4877d 09h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4890d 11h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4897d 21h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4917d 17h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4917d 17h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4917d 17h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4918d 18h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4918d 18h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4918d 20h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4919d 09h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4920d 17h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4921d 07h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4921d 13h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4922d 09h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4923d 20h /versatile_library/trunk/rtl/verilog/
17 unneback 4987d 09h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4993d 17h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4993d 22h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4994d 00h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4994d 20h /versatile_library/trunk/rtl/verilog/

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