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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 104

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Rev Log message Author Age Path
104 versatile_mem modules naming unneback 4864d 10h /versatile_mem_ctrl/
103 added new block diagram pictures and texi source unneback 4893d 04h /versatile_mem_ctrl/
102 cleaning up unneback 4895d 10h /versatile_mem_ctrl/
101 cleaning up unneback 4895d 10h /versatile_mem_ctrl/
100 unneback 4895d 10h /versatile_mem_ctrl/
99 updated stimuli with automatic check unneback 4895d 11h /versatile_mem_ctrl/
98 updates unneback 4998d 15h /versatile_mem_ctrl/
97 updated tb and sdram16 unneback 4999d 04h /versatile_mem_ctrl/
96 doc update unneback 5029d 16h /versatile_mem_ctrl/
95 new files unneback 5034d 05h /versatile_mem_ctrl/
94 new TB unneback 5042d 13h /versatile_mem_ctrl/
93 unneback 5053d 10h /versatile_mem_ctrl/
92 unneback 5053d 10h /versatile_mem_ctrl/
91 unneback 5053d 10h /versatile_mem_ctrl/
90 unneback 5053d 10h /versatile_mem_ctrl/
89 unneback 5053d 10h /versatile_mem_ctrl/
88 unneback 5053d 10h /versatile_mem_ctrl/
87 unneback 5053d 11h /versatile_mem_ctrl/
86 mikaeljf 5105d 18h /versatile_mem_ctrl/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5106d 18h /versatile_mem_ctrl/
84 mikaeljf 5110d 17h /versatile_mem_ctrl/
83 mikaeljf 5111d 12h /versatile_mem_ctrl/
82 mikaeljf 5111d 16h /versatile_mem_ctrl/
81 mikaeljf 5112d 13h /versatile_mem_ctrl/
80 mikaeljf 5112d 14h /versatile_mem_ctrl/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5150d 04h /versatile_mem_ctrl/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5152d 11h /versatile_mem_ctrl/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5160d 09h /versatile_mem_ctrl/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5165d 10h /versatile_mem_ctrl/
75 mikaeljf 5165d 11h /versatile_mem_ctrl/

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