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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 35

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Rev Log message Author Age Path
35 work for limited test case unneback 5231d 10h /versatile_mem_ctrl/
34 added unneback 5231d 10h /versatile_mem_ctrl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5231d 12h /versatile_mem_ctrl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5234d 16h /versatile_mem_ctrl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 09h /versatile_mem_ctrl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 09h /versatile_mem_ctrl/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5240d 09h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5240d 11h /versatile_mem_ctrl/
27 unneback 5244d 03h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5246d 02h /versatile_mem_ctrl/
25 unneback 5246d 05h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5246d 16h /versatile_mem_ctrl/
23 Removed redundant code. mikaeljf 5254d 09h /versatile_mem_ctrl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5256d 04h /versatile_mem_ctrl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5260d 08h /versatile_mem_ctrl/
20 Minor update of sdc-file. mikaeljf 5262d 09h /versatile_mem_ctrl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5268d 14h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5269d 11h /versatile_mem_ctrl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5272d 09h /versatile_mem_ctrl/
16 Added fizzim.pl mikaeljf 5272d 10h /versatile_mem_ctrl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5273d 10h /versatile_mem_ctrl/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5363d 13h /versatile_mem_ctrl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5363d 15h /versatile_mem_ctrl/
12 Minor update of whishbone FSMs in TB mikaeljf 5373d 16h /versatile_mem_ctrl/
11 Initial version with support for DDR mikaeljf 5374d 04h /versatile_mem_ctrl/
10 unneback 5401d 12h /versatile_mem_ctrl/
9 testbench unneback 5401d 12h /versatile_mem_ctrl/
8 unneback 5497d 08h /versatile_mem_ctrl/
7 unneback 5497d 08h /versatile_mem_ctrl/
6 unneback 5497d 08h /versatile_mem_ctrl/

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