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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 54

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Rev Log message Author Age Path
54 dqm moved into FSM unneback 5225d 18h /versatile_mem_ctrl/
53 unneback 5225d 18h /versatile_mem_ctrl/
52 act exit for read updated unneback 5226d 19h /versatile_mem_ctrl/
51 act exit for read updated unneback 5226d 19h /versatile_mem_ctrl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5226d 22h /versatile_mem_ctrl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5226d 23h /versatile_mem_ctrl/
48 dq_oe fix unneback 5226d 23h /versatile_mem_ctrl/
47 support for registered outputs on ras, cas and we unneback 5227d 00h /versatile_mem_ctrl/
46 cosmetic updates unneback 5227d 01h /versatile_mem_ctrl/
45 added unneback 5227d 03h /versatile_mem_ctrl/
44 registered row comparison unneback 5229d 03h /versatile_mem_ctrl/
43 unneback 5229d 08h /versatile_mem_ctrl/
42 added pipeline stage for egress FIFO readot unneback 5229d 16h /versatile_mem_ctrl/
41 Added two alternate data capture functions. mikaeljf 5230d 00h /versatile_mem_ctrl/
40 updated fifo interfaces with re/rd and we/wr unneback 5230d 07h /versatile_mem_ctrl/
39 updated FIFO and SDR 16 unneback 5230d 18h /versatile_mem_ctrl/
38 casex in rw state to save logic unneback 5233d 02h /versatile_mem_ctrl/
37 unneback 5233d 16h /versatile_mem_ctrl/
36 unneback 5233d 17h /versatile_mem_ctrl/
35 work for limited test case unneback 5234d 00h /versatile_mem_ctrl/
34 added unneback 5234d 01h /versatile_mem_ctrl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5234d 03h /versatile_mem_ctrl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5237d 07h /versatile_mem_ctrl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 00h /versatile_mem_ctrl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 00h /versatile_mem_ctrl/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5243d 00h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5243d 02h /versatile_mem_ctrl/
27 unneback 5246d 17h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5248d 16h /versatile_mem_ctrl/
25 unneback 5248d 19h /versatile_mem_ctrl/

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