OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 73

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5190d 17h /versatile_mem_ctrl/
72 Restored lost revisions 69 and 70. mikaeljf 5190d 17h /versatile_mem_ctrl/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5190d 18h /versatile_mem_ctrl/
70 mikaeljf 5194d 00h /versatile_mem_ctrl/
69 mikaeljf 5194d 21h /versatile_mem_ctrl/
68 cleaqnup unneback 5196d 09h /versatile_mem_ctrl/
67 added FSM for wb if unneback 5196d 09h /versatile_mem_ctrl/
66 unneback 5196d 12h /versatile_mem_ctrl/
65 added unneback 5196d 12h /versatile_mem_ctrl/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5197d 12h /versatile_mem_ctrl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5197d 19h /versatile_mem_ctrl/
62 Added note to sdr_16_defines.v asking if it's still used julius 5197d 21h /versatile_mem_ctrl/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5201d 19h /versatile_mem_ctrl/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5201d 19h /versatile_mem_ctrl/
59 counter changed to shift register unneback 5201d 21h /versatile_mem_ctrl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5202d 22h /versatile_mem_ctrl/
57 added support for early termination of burst access unneback 5204d 01h /versatile_mem_ctrl/
56 corrected fifo_rd_data in state w4d unneback 5205d 17h /versatile_mem_ctrl/
55 Fixed up sdr16 dqm output julius 5206d 12h /versatile_mem_ctrl/
54 dqm moved into FSM unneback 5207d 09h /versatile_mem_ctrl/
53 unneback 5207d 09h /versatile_mem_ctrl/
52 act exit for read updated unneback 5208d 11h /versatile_mem_ctrl/
51 act exit for read updated unneback 5208d 11h /versatile_mem_ctrl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5208d 13h /versatile_mem_ctrl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5208d 15h /versatile_mem_ctrl/
48 dq_oe fix unneback 5208d 15h /versatile_mem_ctrl/
47 support for registered outputs on ras, cas and we unneback 5208d 16h /versatile_mem_ctrl/
46 cosmetic updates unneback 5208d 16h /versatile_mem_ctrl/
45 added unneback 5208d 19h /versatile_mem_ctrl/
44 registered row comparison unneback 5210d 19h /versatile_mem_ctrl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.