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[/] [versatile_mem_ctrl/] - Rev 79

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Rev Log message Author Age Path
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5171d 10h /versatile_mem_ctrl/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5173d 17h /versatile_mem_ctrl/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5181d 15h /versatile_mem_ctrl/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5186d 16h /versatile_mem_ctrl/
75 mikaeljf 5186d 17h /versatile_mem_ctrl/
74 Minor update of rtl Makefile. mikaeljf 5190d 16h /versatile_mem_ctrl/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5190d 17h /versatile_mem_ctrl/
72 Restored lost revisions 69 and 70. mikaeljf 5190d 18h /versatile_mem_ctrl/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5190d 19h /versatile_mem_ctrl/
70 mikaeljf 5194d 01h /versatile_mem_ctrl/
69 mikaeljf 5194d 22h /versatile_mem_ctrl/
68 cleaqnup unneback 5196d 10h /versatile_mem_ctrl/
67 added FSM for wb if unneback 5196d 10h /versatile_mem_ctrl/
66 unneback 5196d 13h /versatile_mem_ctrl/
65 added unneback 5196d 13h /versatile_mem_ctrl/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5197d 12h /versatile_mem_ctrl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5197d 20h /versatile_mem_ctrl/
62 Added note to sdr_16_defines.v asking if it's still used julius 5197d 22h /versatile_mem_ctrl/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5201d 20h /versatile_mem_ctrl/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5201d 20h /versatile_mem_ctrl/
59 counter changed to shift register unneback 5201d 22h /versatile_mem_ctrl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5202d 23h /versatile_mem_ctrl/
57 added support for early termination of burst access unneback 5204d 01h /versatile_mem_ctrl/
56 corrected fifo_rd_data in state w4d unneback 5205d 18h /versatile_mem_ctrl/
55 Fixed up sdr16 dqm output julius 5206d 13h /versatile_mem_ctrl/
54 dqm moved into FSM unneback 5207d 10h /versatile_mem_ctrl/
53 unneback 5207d 10h /versatile_mem_ctrl/
52 act exit for read updated unneback 5208d 12h /versatile_mem_ctrl/
51 act exit for read updated unneback 5208d 12h /versatile_mem_ctrl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5208d 14h /versatile_mem_ctrl/

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